Array Cache Tech LLC v. MediaTek Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Array Cache Technologies, LLC (Texas)
  • Defendant: MediaTek Inc. (China)
  • Plaintiff’s Counsel: Fabricant LLP
• Case Identification: 2:25-cv-00669, E.D. Tex., 06/30/2025
• Venue Allegations: Venue is alleged to be proper because the defendant is a foreign company, which may be sued in any judicial district, and because Defendant allegedly transacts substantial business and commits acts of infringement in the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s Systems-on-Chip (SoCs), which are used in mobile devices and other electronics, infringe a patent related to dynamically enforcing store atomicity in multi-core processor architectures.
• Technical Context: The technology concerns memory consistency models in high-performance computer processors, a critical field for ensuring both speed and program correctness in modern multi-core CPUs and GPUs.
• Key Procedural History: The complaint asserts that the technology of the patent-in-suit was originally developed by individuals at Eta Scale AB. The complaint alleges that Defendant has had knowledge of its infringement since at least 2019. No prior litigation or post-grant proceedings are mentioned in the complaint.

Case Timeline

Date	Event
2018-12-14	’485 Patent Priority Date
2019-01-01	Alleged earliest date of Defendant's knowledge
2022-05-17	’485 Patent Issue Date
2025-06-30	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,334,485 - "System and Method for Dynamic Enforcement of Store Atomicity," issued May 17, 2022

The Invention Explained

• Problem Addressed: In modern multi-core processors, performance is often improved by relaxing memory ordering rules. For example, a technique called "store-to-load forwarding" allows a processor core to read a value it just wrote to a temporary "store buffer" before that value has been made visible to all other cores. However, this can lead to a "store atomicity violation," where different cores effectively see memory updates in different orders, potentially causing program errors or system instability ('485 Patent, col. 1:25-58).
• The Patented Solution: The invention proposes a method to dynamically manage this risk. When a core performs store-to-load forwarding, any subsequent load instructions on that same core are assigned a "speculative" status. These speculative loads are prevented from being finalized ("committing") until the original store operation that was forwarded is complete and globally visible. If a conflicting memory event occurs in the interim, the speculative load can be canceled and re-executed ("squashed"), thus preserving system-wide data consistency while still allowing the performance benefits of forwarding in non-conflicting situations ('485 Patent, Abstract; col. 2:23-35). The operation of this mechanism is illustrated through a "commit gate" that controls when loads can finalize ('485 Patent, Figs. 3-5).
• Technical Importance: This approach seeks to balance the conflicting demands of performance and correctness in multi-core systems by enforcing strict ordering only when a potential violation is detected, rather than imposing a constant performance penalty. ('485 Patent, col. 2:1-7).

Key Claims at a Glance

• The complaint asserts at least independent method claim 7 (Compl. ¶15).
• The essential elements of independent claim 7 are:
  • Executing a given processor core load associated with a first memory location.
  • Receiving data for that load from an existing processor core store that is associated with the same memory location and is located in a store buffer.
  • Assigning a speculative state to a subsequent load to prevent it from committing before the existing store is performed globally.
• The complaint does not explicitly reserve the right to assert dependent claims, but alleges infringement of "one or more claims" (Compl. ¶20).

III. The Accused Instrumentality

Product Identification

• The Accused Products are MediaTek’s ARM-based Systems-on-Chip (SoCs), including but not limited to the Dimensity, Kompanio, and Pentonic series. The complaint specifically identifies SoCs with Mali-G77 and later GPUs that implement the "Valhall architecture" and/or "CoreLink Cache Coherent Interconnect" technology (Compl. ¶¶10-11).

Functionality and Market Context

• The complaint alleges that the Accused Products implement "dynamic enforcement of store atomicity in cache coherence for GPU cores" (Compl. ¶15). The complaint points to the architecture of the Mali-G77 GPU, which allegedly uses a load/store unit with an L1 cache for each core, backed by a shared L2 cache, to handle memory operations (Compl. ¶16). A diagram from ARM documentation is included to illustrate the architecture of a Valhall programmable execution core, showing multiple processing units, a message fabric, and a load/store unit with L1 cache (Compl. p. 6, Figure 3-1). These SoCs are described as being incorporated into high-volume consumer electronics, such as smartphones from Motorola and tablets from Samsung (Compl. ¶11).

IV. Analysis of Infringement Allegations

’485 Patent Infringement Allegations

Claim Element (from Independent Claim 7)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
executing a given processor core load at a given time and at a given processor core in a plurality of processor cores, the given processor core load associated with a first memory location;	The GPU of the Dimensity 1100 SoC allegedly comprises multiple processing cores, each executing processor load operations associated with memory addresses within L1 or L2 cache memory (Compl. p. 9, Figure 1).	¶17	col. 14:41-44
receiving data for the given processor core load from an existing processor core store associated with the first memory location and located in a store buffer associated with the given processor core;	The Mali-G77 GPU allegedly performs this function when a processor core "fetches the most recent data from the store buffer after instructions associated with the processor core store are performed." This is tied to the operation of the load/store unit.	¶18	col. 14:57-61
and assigning a speculative state to a subsequent in program order processor core load ... to prevent the subsequent in program order processor core load from committing before the existing processor core store is performed.	The Mali-G77 GPU allegedly "assigns a speculative state to a subsequent program order processor core load ... when executing new instructions while prior high latency instructions are still in flight." The complaint cites documentation stating that in the Valhall architecture, the compiler must explicitly insert a dependency to wait on a previous instruction (Compl. p. 10).	¶19	col. 8:39-54

• Identified Points of Contention:
  • Scope Questions: A central dispute may concern whether the accused Valhall architecture's method for handling "dependencies" (Compl. p. 10) meets the claim limitation of "assigning a speculative state." The patent defines a specific "SA-Speculative" state triggered by a store-to-load forwarding event ('485 Patent, col. 8:39-42). The complaint's evidence describes a more general compiler-managed dependency to hide latency. This raises the question of whether the general-purpose latency-hiding mechanism of the accused devices is equivalent to the specific, event-driven speculative state claimed in the patent.
  • Technical Questions: The infringement theory depends on linking three distinct events in the accused devices: (1) a store-to-load forward, (2) the assignment of a special status to a different, subsequent load, and (3) the prevention of that subsequent load's finalization. The complaint alleges that this sequence occurs (Compl. ¶¶18-19), but the supporting documentation primarily discusses general dependency management. The case may turn on what evidence can demonstrate that the accused processors' behavior is caused by the specific sequence required by the claim, rather than by a more generic instruction scheduling and dependency resolution process.

V. Key Claim Terms for Construction

The Term: "store buffer"

• Context and Importance: The claimed method is initiated when a load receives data from a store residing in a "store buffer." The complaint alleges infringement by devices with a "load/store unit" and L1/L2 caches but does not explicitly identify a "store buffer" in the accused architecture (Compl. ¶16). The definition of this term will be critical to determining if the accused architecture contains the structure required to perform the claimed method.
• Evidence for a Broader Interpretation: The patent specification describes the store buffer as a structure for holding executed but not-yet-performed stores, and notes that in some architectures it can be a single physical structure with a "store queue (SQ)" for uncommitted stores and a "store buffer (SB)" for committed ones ('485 Patent, col. 5:31-44). This could support an argument that the term encompasses modern, complex load/store units that temporarily hold store data.
• Evidence for a Narrower Interpretation: The patent’s abstract and claims refer to a "separate store buffer" ('485 Patent, Abstract; col. 16:6-12). This could support a narrower construction requiring a physically or logically distinct hardware component, which a defendant might argue its integrated load/store unit is not.

The Term: "speculative state"

• Context and Importance: The core of the invention is the assignment of a "speculative state." The infringement case hinges on mapping this claim term onto the accused products' alleged handling of instruction dependencies (Compl. ¶19). Practitioners may focus on this term because its construction will determine whether a general latency-hiding feature can infringe a claim for a specific error-prevention mechanism.
• Evidence for a Broader Interpretation: The claim uses the general term "a speculative state," not a more specific term like the "SA-Speculative" state that is detailed in the patent's description ('485 Patent, col. 8:39-42). This may support an interpretation that any state in which a load is prevented from committing due to an unresolved, older memory operation falls within the claim's scope.
• Evidence for a Narrower Interpretation: The specification provides a very precise definition for its novel form of speculation, "Store-Atomicity Speculative (SA-Speculative)," which is directly tied to a preceding store-to-load forwarding event ('485 Patent, col. 8:39-42). A defendant may argue that "speculative state" in the context of the patent should be limited to this specific type of speculation, and that the accused devices' more general dependency management does not meet this narrower definition.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement, stating that MediaTek provides customers and end-users with "instruction manuals, websites, promotional materials, [and] advertisements" that instruct on the use of the accused SoCs in an infringing manner (Compl. ¶21). It further alleges contributory infringement, arguing the accused components are a material part of the invention, are not staple articles of commerce, and are known to be especially adapted for infringement (Compl. ¶22).
• Willful Infringement: Willfulness is alleged based on Defendant’s purported knowledge of the ’485 Patent and the infringing nature of its products "since at least 2019 but by no later than the date of this Complaint" (Compl. ¶21). The complaint also makes a general allegation that MediaTek has known of Array Cache's patents (Compl. ¶24).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "speculative state," as used in Claim 7, be construed to cover the accused Valhall architecture's general-purpose dependency management for hiding memory latency, or is it limited by the specification to the more specific "SA-Speculative" state triggered only by a store-to-load forwarding event?
• A key evidentiary question will be one of functional mapping: can the plaintiff demonstrate that the accused SoCs' "load/store unit" and associated caches function as the claimed "store buffer," and that this structure's operation causes the specific three-step sequence of (1) forwarding, (2) assignment of a state to a subsequent load, and (3) prevention of that load's commitment, as required by the claim?