DCT

2:25-cv-00748

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00748, E.D. Tex., 07/28/2025
  • Venue Allegations: Venue is alleged based on Samsung entities maintaining a regular and established place of business in Plano, Texas, and Avnet maintaining one in Richardson, Texas, both within the Eastern District of Texas, where acts of infringement have allegedly occurred. The complaint also notes that Samsung has not contested venue in prior litigation in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s DDR5 memory modules, which feature on-module power management, infringe a patent related to the same technology.
  • Technical Context: The lawsuit concerns high-performance computer memory (DDR5 DIMMs), a critical component in servers for cloud computing and artificial intelligence, where moving power management circuitry onto the memory module itself represents a key architectural evolution.
  • Key Procedural History: The complaint details a long and contentious litigation history between the parties, including multiple prior patent infringement lawsuits in the Eastern District of Texas resulting in jury verdicts against Samsung in 2023 and 2024. It also references parallel contract litigation in California concerning a 2015 Joint Development and License Agreement (JDLA) that Netlist terminated in 2020. The complaint asserts that Samsung had pre-suit knowledge of the patent-in-suit at least as of May 17, 2022, due to an inter partes review (IPR) proceeding Samsung initiated.

Case Timeline

Date Event
2007-06-01 '366 Patent Priority Date
2022-05-17 Samsung's alleged pre-suit knowledge of '366 Patent via IPR filing
2023-04-21 Jury verdict in prior Netlist v. Samsung patent case
2024-05-17 Jury verdict in Netlist v. Samsung contract case
2024-05-23 Jury verdict in Netlist v. Micron patent case
2024-11-22 Jury verdict in prior Netlist v. Samsung patent case
2025-03-24 Jury verdict in Netlist v. Samsung contract case retrial
2025-07-28 Complaint Filing Date
2025-07-29 '366 Patent Issue Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,373,366 - "Memory with On-Module Power Management"

  • Issued: July 29, 2025

The Invention Explained

  • Problem Addressed: The patent’s background section describes the performance bottleneck created when a high-speed Central Processing Unit (CPU) must transfer data to and from comparatively slower memory and storage subsystems, limiting overall system performance. (’366 Patent, col. 1:35-40).
  • The Patented Solution: The invention is a memory module (DIMM) that integrates its own power management circuitry directly onto the module's printed circuit board. As described in the patent, this on-module system uses multiple converter circuits to receive an input voltage and generate several different regulated voltages for the module's components, such as the SDRAM memory chips. The module also includes a voltage monitor circuit that can detect a power anomaly (e.g., an overvoltage condition) and trigger a protective action, such as writing data to on-board non-volatile memory. (’366 Patent, Abstract; col. 4:8-23).
  • Technical Importance: Moving power management from the computer's motherboard onto the memory module itself allows for more precise voltage control, which is necessary to support the higher data rates of newer memory technologies like DDR5. (Compl. ¶32).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶22).
  • The essential elements of independent claim 1 are:
    • A dual in-line memory module (DIMM) with a printed circuit board (PCB) having edge connections for power, data, and control signals, where the power from the system board is the only power received.
    • A "controller" on the PCB that includes a voltage monitor circuit and nonvolatile memory. The monitor is configured to detect a trigger condition (e.g., input voltage exceeding a threshold) and, in response, cause the controller to write data into the nonvolatile memory.
    • A set of components on the PCB, including DDR synchronous dynamic random access memory (SDRAM) devices.
    • Four distinct converter circuits on the PCB that receive power and deliver four regulated voltage lines to the set of components.
    • The SDRAM devices are arranged in at least two groups (a first of at least five devices, a second of at least four), where the first group can output at least 40 1-bit data signals (including 32 data bits and 8 error-correcting code bits).

III. The Accused Instrumentality

Product Identification

  • The accused products are broadly defined as "any Samsung DDR5 products," with specific, non-limiting examples including Samsung's DDR5 RDIMMs (Registered DIMMs) and any modules that utilize Samsung's own power management integrated circuits (PMICs), such as those with part numbers S2FPC01, S2FPD01, and S2FPD02. (Compl. ¶29).

Functionality and Market Context

  • The complaint alleges that the accused DDR5 modules incorporate the key architectural shift of moving power management from the motherboard onto the memory module itself. (Compl. ¶32). This is allegedly embodied in an "on-DIMM PMIC" that Samsung's own marketing materials claim "further boosts power management efficiency and power supply stability." (Compl. ¶32).
  • Technically, the accused modules are alleged to feature two independent 40-bit channels, each comprising 32 data bits and 8 error-correcting code (ECC) bits, which improves concurrency and performance over prior generations. (Compl. ¶31). These products are positioned for data-intensive applications like cloud computing and artificial intelligence. (Compl. ¶23).

IV. Analysis of Infringement Allegations

Claim Chart Summary

The complaint alleges infringement of at least claim 1 of the ’366 Patent. The core allegations are summarized below.

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A dual in-line memory module (DIMM) configured to fit into a memory slot connector of a system board... The accused Samsung DDR5 RDIMM products are DIMMs designed to fit into standard memory slot connectors on a computer system's system board. A photograph in the complaint shows such modules installed. (Compl. ¶37). ¶36-37 col. 1:44-50
a printed circuit board (PCB) having edge connections... wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM... The accused DDR5 RDIMM comprises a PCB with "gold fingers" that serve as edge connections. The power is allegedly delivered from the system to an on-module PMIC, and this is the only power the DIMM receives. A diagram illustrates this direct 12V power delivery. (Compl. ¶41). ¶38-41 col. 7:10-17
a controller including a voltage monitor circuit and nonvolatile memory... configured to... generate a trigger signal upon detecting a trigger condition... and perform... a write operation to write data into the nonvolatile memory... The accused Samsung DDR5 RDIMM module allegedly contains a controller (a PMIC) with a voltage monitor and nonvolatile memory. This controller is allegedly configured to monitor input voltage, generate a trigger signal on an overvoltage condition, and initiate actions that include writing to non-volatile memory. An annotated product image identifies the PMIC. (Compl. ¶49). ¶48-55 col. 23:13-24
a set of components coupled to the PCB... including a plurality of... (SDRAM) devices... The accused DDR5 RDIMM comprises a set of components coupled to the PCB, including DDR5 SDRAM memory devices, a register clock driver (RCD), and a PMIC. ¶56-57 col. 22:30-38
first, second, third, and fourth converter circuits coupled to the PCB... configured to... deliver power via first, second, third, and fourth regulated voltage lines... The accused DDR5 RDIMM's PMIC allegedly includes circuitry making up four converter circuits that receive power from an input voltage supply line and deliver four regulated voltage lines to other components on the module. ¶58-59 col. 26:42-49
wherein the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices... and a second group of at least four... configured to... receive or output at least 40 1-bit DDR data signals... The accused DDR5 RDIMM allegedly includes two independent channels (Channel A and B), each with at least five SDRAM devices. Each channel is designed to handle 40-bit DDR data signals (32 data bits plus 8 ECC bits). A diagram from a technical paper is used to illustrate these independent sub-channels. (Compl. ¶70). ¶69-78 col. 39:41-54

Identified Points of Contention

  • Scope Questions: The case may raise questions about whether the accused products literally meet the precise numerical limitations of the claims. For example, the court may need to determine if Samsung's PMIC contains exactly "four converter circuits" as required by claim 1[d], and if its SDRAM layout meets the specific "at least five" and "at least four" device groupings of claim 1[e]. Any deviation could be a basis for a non-infringement argument.
  • Technical Questions: A primary technical question will likely concern the functionality of the claimed "controller." Claim 1[b] requires the controller to be "configured to perform... a write operation to write data into the nonvolatile memory" in response to a voltage trigger. The complaint alleges this function exists (Compl. ¶55), but the court will need to examine evidence of whether Samsung's PMIC performs this specific, hardware-driven sequence, or if it merely flags an error for higher-level software to handle, which may not satisfy the claim language.

V. Key Claim Terms for Construction

  • The Term: "controller"

    • Context and Importance: The infringement theory hinges on equating Samsung's on-module Power Management Integrated Circuit (PMIC) with the patent's "controller" (Compl. ¶49). The claim requires this controller to integrate a voltage monitor, nonvolatile memory, and logic to perform a triggered write operation. The definition of "controller" is therefore critical; if a PMIC is determined to be a mere power regulation chip without the claimed memory and control logic, the infringement allegation for claim 1[b] could fail.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent specification describes that the logic element of the controller can be implemented in various ways, including a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a complex programmable logic device (CPLD), suggesting the term is not limited to a single type of hardware. (’366 Patent, col. 23:13-24).
      • Evidence for a Narrower Interpretation: The patent's abstract and detailed embodiments describe a controller with significant logic capabilities beyond simple power conversion, including managing data transfer, address mapping, and error correction. (’366 Patent, Abstract; col. 13:41-55). This may support a narrower construction requiring a more sophisticated, programmable logic device rather than a standard PMIC.

  • The Term: "wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM"

    • Context and Importance: This negative limitation in claim 1[a] creates a strict condition. Practitioners may focus on this term because if the defense can show that the accused Samsung modules receive any other power from any other source (e.g., a sideband signal for diagnostics, a separate power pin for a minor component), it could defeat a literal infringement allegation.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation (favors non-infringement): The plain language "the only power" is absolute. Any evidence of a second, external power source, regardless of its purpose or magnitude, could support a finding that this limitation is not met.
      • Evidence for a Narrower Interpretation (favors infringement): A court could interpret the term in the context of the invention, which focuses on the architectural shift of the main power delivery for the DRAM and logic. The patent's discussion centers on the main 12V power path being moved onto the DIMM. (’366 Patent, col. 16:3-10). This context might support an interpretation where "power" refers to the primary operational power, potentially excluding de minimis or ancillary power sources not relevant to the core inventive concept.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement to infringe by asserting that Defendants provide "specifications, datasheets, [and] instruction manuals" that encourage customers and distributors to use the accused products in an infringing manner. (Compl. ¶79). It also alleges contributory infringement, claiming the accused DDR5 products are a "material part of the patented invention" and have "no substantial noninfringing uses." (Compl. ¶80).
  • Willful Infringement: The willfulness claim is based on both pre-suit and post-suit knowledge. The complaint alleges Samsung had pre-suit knowledge of the ’366 Patent no later than May 17, 2022, from an IPR proceeding it filed. (Compl. ¶21). Post-suit knowledge is based on the filing of the complaint. (Compl. ¶81). The complaint alleges Defendants continued to infringe despite a "high likelihood" that their actions constituted infringement, creating an "unjustifiably high risk." (Compl. ¶¶81-82).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of functional implementation: does Samsung's on-module PMIC perform the specific, multi-step function recited in claim 1[b]—namely, detecting an overvoltage trigger and, in direct response, autonomously performing a write operation to nonvolatile memory—or does it merely log a status that requires higher-level software intervention, creating a potential mismatch with the claim's requirement that the "controller is configured to perform" the write?
  • A second central question will be one of structural and numerical identity: does the accused DDR5 module's architecture literally meet the precise limitations of claim 1, such as the requirement for "four converter circuits" and the specific SDRAM groupings, or will evidence show a technical deviation that places the product outside the claim's literal scope?
  • Finally, the case may involve a strict examination of the negative limitation in claim 1[a]. The inquiry will focus on whether the accused module receives any power, however minor or for whatever ancillary purpose, from a source other than the system board's main power rails, which could be sufficient to establish non-infringement of this element.