DCT

2:25-cv-00748

Netlist Inc v. Samsung Electronics Co Ltd

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00748, E.D. Tex., 01/04/2026
  • Venue Allegations: Plaintiff alleges venue is proper based on Defendants' alleged commission of infringing acts within the Eastern District of Texas and their maintenance of regular and established places of business in Allen and Richardson, Texas.
  • Core Dispute: Plaintiff alleges that Defendants’ DDR5 memory modules infringe a patent related to on-module power management architecture.
  • Technical Context: The technology concerns high-performance computer memory modules (DIMMs), where on-module power management is a key feature of the DDR5 industry standard, enabling the higher data rates required for server, cloud computing, and artificial intelligence applications.
  • Key Procedural History: The complaint describes a history of litigation between the parties, referencing prior patent infringement suits filed by Netlist against Micron, as well as counterclaims and separate suits filed by Micron against Netlist alleging antitrust violations and bad-faith patent assertion. The complaint also preemptively addresses and denies any breach of RAND (Reasonable and Non-Discriminatory) licensing obligations related to standards set by the JEDEC Solid State Technology Association.

Case Timeline

Date Event
2007-06-01 ’366 Patent Earliest Priority Date
2025-07-29 U.S. Patent No. 12,373,366 Issues
2026-01-04 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,373,366 - *Memory with On-Module Power Management*

  • Patent Identification: U.S. Patent No. 12,373,366 (“Memory with On-Module Power Management”), issued July 29, 2025 (the “’366 Patent”).

The Invention Explained

  • Problem Addressed: As data processing speeds for computer memory increased, managing power delivery from the motherboard to the memory module became a significant challenge. The complaint notes that accommodating the higher data rates of DDR5 memory required more precise voltage control and a reduction in power loss than was achievable with motherboard-based power management (Compl. ¶32).
  • The Patented Solution: The ’366 Patent describes a memory module (DIMM) that integrates power management components directly onto its printed circuit board (PCB) (’366 Patent, Abstract). The invention includes a controller with a voltage monitor circuit that can detect when an input voltage exceeds a threshold (’366 Patent, col. 4:1-15). Upon detecting such a "trigger condition," the controller is configured to perform a write operation to on-module nonvolatile memory, providing a mechanism to save data in response to a power anomaly (’366 Patent, Abstract). The module also features multiple on-board converter circuits to receive a pre-regulated input voltage and deliver several different regulated voltages required by various components on the DIMM (’366 Patent, col. 1:1-8).
  • Technical Importance: This on-module power management architecture is presented in the complaint as a foundational element of the DDR5 memory standard, enabling the performance, reliability, and density improvements over the prior DDR4 generation (Compl. ¶¶31-32).

Key Claims at a Glance

  • The complaint provides a detailed breakdown of independent claim 1 (Compl. ¶26).
  • Essential elements of Claim 1 include:
    • A dual in-line memory module (DIMM) with a PCB and edge connections for power, data, and control signals, where the only power it receives is from the system board power rails.
    • An on-board "controller" that includes a voltage monitor circuit and nonvolatile memory. The circuit is configured to monitor an input voltage, generate a trigger signal if the voltage exceeds a threshold, and in response, perform a write operation to the nonvolatile memory.
    • A plurality of synchronous dynamic random access memory (SDRAM) devices on the PCB.
    • Four distinct converter circuits on the PCB that receive power from an input voltage supply line and deliver four regulated voltage lines to power various components.
    • A specific architectural arrangement of the SDRAM devices, organized into a first group of at least five devices and a second group of at least four devices, connected to separate chip select lines and configured to operate as two independent data channels totaling at least 72 data conduits.
  • The complaint alleges infringement of "at least one claim" of the ’366 Patent (Compl. ¶56).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the accused products as "Accused DDR5 Products," including but not limited to Micron's DDR5 RDIMMs and MRDIMMs, particularly those that utilize Micron's own on-module power management integrated circuits (PMICs) (Compl. ¶29).

Functionality and Market Context

  • The complaint alleges that the accused products are DDR5 memory modules that incorporate key architectural upgrades over the prior DDR4 standard (Compl. ¶31). This includes moving power management from the motherboard onto the module itself via on-board PMICs (Compl. ¶32). A diagram from a Micron technical brief is included to illustrate the layout of a DDR5 module, identifying the PMIC at the center of the PCB between two independent 40-bit subchannels (Compl. p. 24, fig. at ¶71).
  • These modules are allegedly designed for use in servers supporting data-intensive applications such as cloud computing and artificial intelligence (Compl. ¶22). The complaint alleges that Defendant Micron manufactures these products and Defendant Avnet acts as a distributor, offering them for sale in the United States, including within the Eastern District of Texas (Compl. ¶¶9, 17, 28).

IV. Analysis of Infringement Allegations

’366 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A dual in-line memory module (DIMM) configured to fit into a memory slot connector of a system board... The complaint alleges the Accused DDR5 Products are DIMMs designed to be installed in a system board. ¶58-59 col. 1:1-8
a printed circuit board (PCB) having edge connections configured to fit into the memory slot connector...wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM... The complaint alleges the Accused DDR5 Products are PCBs with edge connectors that receive all their operating power from the system board. ¶60-69 col. 2:50-55
a controller including a voltage monitor circuit and nonvolatile memory...the voltage monitor circuit configured to: (i) monitor an input voltage... (ii) generate a trigger signal...and (iii) transmit the trigger signal...to perform...a write operation to write data into the nonvolatile memory... The complaint alleges the on-module PMIC in the Accused DDR5 Products functions as the claimed "controller," monitoring input voltage and, upon detecting an overvoltage, initiating a write operation to nonvolatile memory. ¶70-77 col. 4:1-15
a set of components coupled to the PCB, the set of components including a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices... The complaint alleges the Accused DDR5 Products include multiple DDR SDRAM devices on the PCB. ¶78-79 col. 4:50-55
first, second, third, and fourth converter circuits coupled to the PCB...configured to...deliver power via first, second, third, and fourth regulated voltage lines... The complaint alleges the PMIC on the Accused DDR5 Products includes at least four converter circuits that deliver regulated voltages to other components on the module. ¶80-90 col. 1:1-8
...the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices...and a second group of at least four DDR SDRAM devices...configured to receive or output at least 40 1-bit DDR data signals... The complaint alleges the Accused DDR5 Products have an architecture with two independent 40-bit channels, each with a group of SDRAM devices matching the claim's configuration. ¶91-100 col. 4:50-60

Identified Points of Contention

  • Scope Questions: Claim 1 requires that the only power received by the DIMM is from the power rails of the system board. The defense may question whether the complaint sufficiently proves this negative limitation, suggesting the possibility of other incidental power or signal paths that could place the accused products outside the claim's scope. Additionally, a central point of dispute may be whether the accused on-module PMIC meets all the functional requirements of the claimed "controller."
  • Technical Questions: The complaint alleges that the accused PMIC, upon detecting an overvoltage, performs actions that "include updating memory spaces in the non-volatile memory" (Compl. ¶77). A key question for the court will be what evidence demonstrates that the accused PMIC is configured to perform the specific function of writing data to nonvolatile memory in response to a voltage trigger, as required by claim 1, rather than a more conventional power-down or protection sequence. The complaint uses a functional block diagram from a Micron datasheet to support its allegations regarding the converter circuits (Compl. p. 27, fig. at ¶81), and the defense may contest whether this general diagram accurately represents the specific operation required by the claim.

V. Key Claim Terms for Construction

  • The Term: "controller"

    • Context and Importance: This term is central to the invention's novelty. The complaint equates the accused products' PMIC with the claimed "controller" (Compl. ¶71). Practitioners may focus on this term because the defense could argue that a standard PMIC, designed for power regulation, is not a "controller" in the patent's sense, which is explicitly defined as performing a logical sequence of monitoring voltage, detecting a condition, and initiating a write operation to nonvolatile memory.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification may describe the "controller" in broad functional terms as a circuit that manages on-module power and related events, which could support its application to a sophisticated PMIC (’366 Patent, col. 4:1-5).
      • Evidence for a Narrower Interpretation: The claim language itself links the "controller" to a specific three-step function (monitor, trigger, write to nonvolatile memory) (’366 Patent, col. 10:1-11). The defense may argue that this functional requirement narrows the term to a device with specific logic and data-writing capabilities not present in a conventional PMIC.

  • The Term: "wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM"

    • Context and Importance: This "only" limitation provides a potential avenue for a non-infringement defense. The defendant may argue that this negative limitation requires a strict interpretation, and any other incidental electrical input to the DIMM, such as through certain signal pins, would avoid infringement.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A court may construe this term to mean the sole source of operating power, distinguishing it from minor power transferred via data or control signals. The complaint supports this by showing the DIMM fitting into a motherboard slot to receive power (Compl. p. 21, fig. at ¶59).
      • Evidence for a Narrower Interpretation: The plain language of the claim supports a literal interpretation. The defense may argue that if any electrical potential is provided to the DIMM through a path other than the specified "power rails," the limitation is not met.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement based on Defendants providing "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing uses" of the accused products (Compl. ¶101). It also alleges contributory infringement, stating that the accused products have "no substantial noninfringing uses" and constitute a material part of the invention (Compl. ¶102).
  • Willful Infringement: The complaint alleges that both Micron and Avnet have had actual notice of the ’366 Patent "since at least the filing of this Complaint" (Compl. ¶¶103, 104). This allegation appears to be based on post-suit knowledge, which may support a claim for willful infringement from the date of service forward.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A key technical question will be one of functional operation: does the accused Power Management Integrated Circuit (PMIC), which is designed for voltage regulation, also perform the specific, multi-step logical sequence required by the term "controller" in Claim 1—namely, detecting an overvoltage condition and, in response, executing a write operation to nonvolatile memory?
  • A central issue of claim construction will be one of definitional scope: can the term "controller," as defined by its functions in the claim, be construed to read on a standard PMIC, or does the claim require a component with more advanced, programmable logic for data management that is distinct from power regulation?
  • A critical evidentiary question will be one of architectural conformity: do the specific configurations of Micron's various accused DDR5 modules, including SDRAM device counts per chip select line and the total number of data conduits, precisely match the detailed numerical and structural requirements laid out in claim 1?