DCT

2:25-cv-00749

Netlist Inc v. Micron Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00749, E.D. Tex., 07/28/2025
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants have committed acts of infringement in the district and maintain regular and established places of business in Allen and Richardson, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s DDR5 memory modules infringe a patent related to on-module power management architectures.
  • Technical Context: The technology concerns high-performance computer memory modules (DIMMs) that integrate their own power management, a key feature of the industry-standard DDR5 specification for servers and data centers.
  • Key Procedural History: The complaint describes a history of litigation between the parties, referencing prior jury verdicts in the Eastern District of Texas against Micron and other companies on unrelated patents. It also notes that Netlist is seeking a declaration that its assertion of the patent-in-suit is not in bad faith under Idaho state law, in response to what it characterizes as retaliatory suits filed by Micron.

Case Timeline

Date Event
2007-06-01 Earliest Priority Date for ’366 Patent
2025-07-28 Complaint Filing Date
2025-07-29 Issue Date for ’366 Patent

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,373,366 - "Memory with On-Module Power Management"

  • Patent Identification: U.S. Patent No. 12,373,366, "Memory with On-Module Power Management", issued July 29, 2025.

The Invention Explained

  • Problem Addressed: The patent background describes the data transfer bottleneck between high-speed CPUs and relatively slower memory subsystems, a persistent challenge in computer architecture that limits overall system performance (’366 Patent, col. 1:41-col. 2:40).
  • The Patented Solution: The invention moves power management functions from the computer’s main system board directly onto the memory module itself. The patent describes a dual in-line memory module (DIMM) with on-board converter circuits to generate multiple regulated voltages for its components, all managed by an on-module controller that includes a voltage monitor (’366 Patent, Abstract; Fig. 12). This architecture allows for more precise voltage control, which is critical for high-speed memory, and enables the controller to detect power anomalies and trigger protective actions, such as writing data to non-volatile memory.
  • Technical Importance: This on-module power management approach was a foundational shift for the memory industry, enabling the higher data rates and improved power efficiency required by the DDR5 memory standard (Compl. ¶32).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶¶26, 34).
  • The essential elements of Claim 1 include:
    • A dual in-line memory module (DIMM) comprising a printed circuit board (PCB) with edge connections for power, data, and address/control signals.
    • A requirement that the power delivered from the system board's power rails is the only power the DIMM receives.
    • A controller on the PCB that includes both a voltage monitor circuit and nonvolatile memory.
    • The controller is configured to monitor an input voltage, generate a trigger signal if the voltage exceeds a threshold, and in response, perform a write operation to the nonvolatile memory.
    • A set of four distinct converter circuits on the PCB that receive power from an input voltage supply line and deliver four different regulated voltage lines to other components on the module.
    • A plurality of DDR SDRAM devices arranged in at least two groups, connected to distinct chip select lines, and configured to operate over a data bus of at least 72 conduits.

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are Defendants' DDR5 memory products, including but not limited to Micron DDR5 Registered DIMMs (RDIMMs) and Multiplexer-on-DIMM (MRDIMM) modules (Compl. ¶¶29, 34).

Functionality and Market Context

  • The complaint alleges that accused DDR5 modules incorporate on-module power management integrated circuits (PMICs) to achieve the more precise voltage control needed for their high data rates (Compl. ¶32). A key feature of the accused DDR5 architecture is the use of two independent 40-bit channels (32 data bits + 8 ECC bits), which improves concurrency and bandwidth over prior DDR4 technology (Compl. ¶31). These modules are marketed for high-performance applications like servers, cloud computing, and artificial intelligence (Compl. ¶22). The complaint provides an image from a distributor's website showing a specific accused product, the Micron MTC40F2046S1RC56BD1 64GB RDIMM, offered for sale (Compl. ¶17 & p. 7).

IV. Analysis of Infringement Allegations

'366 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a printed circuit board (PCB) having edge connections configured to fit into the memory slot connector of the system board... wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM; The accused DDR5 RDIMM is a PCB with edge connections ("gold fingers") that fit into a system board's memory slot. The complaint alleges the DIMM power supply is delivered from the system to the on-module PMIC and is the only power received. ¶¶38-41 col. 38:5-18
a controller including a voltage monitor circuit and nonvolatile memory...the voltage monitor circuit configured to: (i) monitor an input voltage... (ii) generate a trigger signal... (iii) transmit the trigger signal to at least one other portion of the controller...to perform...a write operation to write data into the nonvolatile memory... The accused DDR5 RDIMM's on-module PMIC is alleged to be the claimed controller, which includes a voltage monitor and nonvolatile memory. The PMIC allegedly monitors the input voltage (e.g., Vin_Bulk) and, upon an overvoltage condition, generates and transmits a trigger signal internally to circuitry that performs actions including updating non-volatile memory. ¶¶48-55 col. 39:1-13
first, second, third, and fourth converter circuits coupled to the PCB... and configured to... deliver power via first, second, third, and fourth regulated voltage lines, The accused DDR5 RDIMM's PMIC is alleged to comprise circuitry for four converter circuits that receive power from an input voltage supply line and deliver four regulated voltages (e.g., VDD, VDDQ, VPP, and a LDO voltage) to various components on the module. ¶¶58-67 col. 39:22-35
wherein the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices... a second group of at least four DDR SDRAM devices... wherein the sum of the... data lines... equals a total number of data conduits... of at least 72 data conduits. The accused DDR5 RDIMM module allegedly includes two independent channels (A and B), each containing at least five SDRAM devices (in x8 configurations). These channels are connected to separate chip select signals and each outputs 40 bits of data, for a total of 80 data conduits, which exceeds the required 72. A functional block diagram from a Micron technical brief is presented as evidence for this architecture. ¶¶69-78, Fig. on p. 24 col. 39:43-col. 40:6
  • Identified Points of Contention:
    • Scope Questions: A central dispute may arise over the term "controller including a... nonvolatile memory." The complaint alleges the PMIC is the controller and that it includes nonvolatile memory (Compl. ¶49). The defense may argue that the PMIC is a distinct component from any nonvolatile memory it may communicate with, which could raise the question of whether the accused product meets this integrated structural limitation.
    • Technical Questions: The complaint alleges that upon a trigger condition, the PMIC initiates actions that include updating nonvolatile memory (Compl. ¶55). A key factual question will be what the accused PMIC actually does. The infringement analysis may turn on whether writing to "real time status registers" (Compl. ¶55) constitutes the claimed "write operation to write data into the nonvolatile memory," or if this alleged functionality is a mischaracterization of a standard overvoltage protection circuit that does not perform the claimed data-write function.

V. Key Claim Terms for Construction

  • The Term: "the only power received by the DIMM"

  • Context and Importance: This is a negative limitation, meaning its scope is absolute. Proving infringement requires showing the absence of any other power source on the DIMM. Practitioners may focus on this term because any evidence of an alternative power pathway, however minor (e.g., for auxiliary functions), could potentially defeat a literal infringement allegation for the entire claim.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent does not appear to provide language suggesting this term means anything other than its plain meaning. A plaintiff might argue that incidental or de minimis power pathways unrelated to the core operation do not vitiate the claim's purpose.
    • Evidence for a Narrower Interpretation: The claim language itself, "the only power," is stark and unambiguous (’366 Patent, col. 38:16-18). The specification does not appear to qualify this language, suggesting it should be given its plain and narrow meaning, which would require the exclusion of all other external power sources.

  • The Term: "write operation to write data into the nonvolatile memory"

  • Context and Importance: The viability of the infringement claim depends on whether the accused PMIC's actual function can be mapped to this claim element. The complaint's theory connects an overvoltage trigger to updating nonvolatile memory via "real time status registers" (Compl. ¶55). The construction of "write operation" will determine if this indirect or status-logging activity meets the claim's requirement.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent's abstract and detailed description focus on preserving data in the event of a power event, suggesting that any mechanism that achieves this data-saving goal in response to a trigger could be considered a "write operation" in the context of the invention.
    • Evidence for a Narrower Interpretation: The patent describes a system for backing up volatile memory to non-volatile memory (’366 Patent, col. 23:25-30). A defendant may argue that "write operation" must be construed in this context to mean a substantive data backup, not merely logging a status code in a register, which may be a fundamentally different technical function.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement, stating that Defendants provide datasheets and instruction manuals that encourage and facilitate the infringing use of the DDR5 products by customers (Compl. ¶79). It also alleges contributory infringement, asserting that the accused products are a material part of the patented invention and have no substantial non-infringing uses (Compl. ¶80).
  • Willful Infringement: Willfulness is alleged against both Micron and Avnet based on knowledge of the ’366 Patent obtained "since at least the filing of this Complaint" (Compl. ¶¶81-82). This establishes a basis for potential post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of structural and functional correspondence: does the accused DDR5 module's PMIC, as a matter of fact, perform the specific function of writing data to an included non-volatile memory in response to a voltage trigger as claimed, or is there a fundamental mismatch between the accused product's architecture and the patent's specific data-preservation system?
  • A key legal question will be one of claim construction: can the phrase "controller including a... nonvolatile memory" be interpreted to cover an architecture where the PMIC and non-volatile memory are physically separate components, or does the claim require an integrated device that is not present in the accused products?
  • A critical evidentiary question will revolve around the negative limitation: what evidence can be adduced to prove that the power supplied from the system board is "the only power received by the DIMM," a requirement that invites intense scrutiny of the accused product's design for any ancillary power circuits.