DCT

2:25-cv-00766

Induction Devices LLC v. Gap Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00766, E.D. Tex., 08/05/2025
  • Venue Allegations: Venue is alleged based on Defendants having committed acts of infringement and maintaining a regular and established place of business within the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendants’ provision and support of branded contactless consumer credit cards indirectly infringes five U.S. patents related to fundamental semiconductor circuit design and operation.
  • Technical Context: The patents-in-suit address core challenges in modern integrated circuits, including reliable system resets, clock signal integrity, secure data handling for near-field communication, asynchronous data transfer, and digital signal processing.
  • Key Procedural History: The complaint notes that U.S. Patent No. 7,899,145 was previously litigated in the Western District of Texas, but those cases were resolved before any substantive matters were addressed, suggesting the patent's claims have not previously undergone judicial construction or validity analysis.

Case Timeline

Date Event
2005-09-02 ’145 Patent Priority Date
2006-01-26 ’926 Patent Priority Date
2006-12-21 ’885 Patent Priority Date
2007-03-09 ’543 Patent Priority Date
2007-04-17 ’628 Patent Priority Date
2008-11-11 ’926 Patent Issue Date
2011-03-01 ’145 Patent Issue Date
2012-05-29 ’885 Patent Issue Date
2013-02-05 ’543 Patent Issue Date
2013-09-24 ’628 Patent Issue Date
2025-08-05 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - *"Circuit for Asynchronously Resetting Synchronous Circuit"*

  • Patent Identification: U.S. Patent No. 7,449,926, "Circuit for Asynchronously Resetting Synchronous Circuit", issued November 11, 2008.

The Invention Explained

  • Problem Addressed: The patent describes a dilemma in resetting synchronous circuits like CPUs. An asynchronous reset is needed for immediate initialization when a circuit operates abnormally, but such a reset during normal operation can cause data loss in memory components like RAM (’926 Patent, col. 1:36-44). Prior art reset circuits did not adequately distinguish between these states to apply the correct type of reset (’926 Patent, col. 2:51-61).
  • The Patented Solution: The invention is a reset signal generation circuit that actively detects whether a synchronous circuit is operating "normally" or "abnormally." Based on this detection, a signal control circuit generates a synchronous reset signal (timed with the system clock to preserve data) during normal operation, or an asynchronous reset signal (immediate, irrespective of the clock) during abnormal operation to ensure a swift and safe reset (’926 Patent, col. 6:58-7:6).
  • Technical Importance: This selective approach enhances the reliability of semiconductor devices by applying the appropriate reset strategy for different operating conditions, balancing the need for data integrity with the need for immediate recovery from system faults (Compl. ¶14).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶35).
  • Essential elements of claim 1 include:
    • An operation detection circuit for detecting whether the synchronous circuit is operating normally or abnormally and for generating an operation detection signal.
    • A signal control circuit for generating a first reset signal based on a system reset signal, the clock signal, and the operation detection signal.
    • The signal control circuit generates the first reset signal synchronously to the clock signal when the synchronous circuit is operating normally.
    • The signal control circuit generates the first reset signal asynchronously to the clock signal when the synchronous circuit is operating abnormally.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,899,145 - *"Circuit, System, and Method for Multiplexing Signals with Reduced Jitter"*

  • Patent Identification: U.S. Patent No. 7,899,145, "Circuit, System, and Method for Multiplexing Signals with Reduced Jitter", issued March 1, 2011.

The Invention Explained

  • Problem Addressed: In complex electronic systems, multiplexing clock signals from different sources (like phase-locked loops or PLLs) can introduce crosstalk and power supply noise, which increases signal "jitter" (timing variations) and degrades system performance and reliability (’145 Patent, col. 2:53-67; Compl. ¶19).
  • The Patented Solution: The patent describes an improved multiplexer architecture where the constituent logic gates are physically and electrically isolated from each other in separate "power supply domains." A logic block deactivates all but one input signal path at a time, ensuring that the downstream logic gates only receive one active signal, thereby eliminating crosstalk and noise injection from the inactive paths (’145 Patent, col. 3:13-34; Compl. ¶20).
  • Technical Importance: This design mitigates a key source of jitter in high-speed clock distribution networks, improving the timing precision and reliability of synchronous systems (’145 Patent, col. 3:1-7).

Key Claims at a Glance

  • The complaint asserts at least independent claim 10 (Compl. ¶45).
  • Essential elements of claim 10 include:
    • A circuit comprising two logic gates and a first logic block and a second logic block, each arranged within a separate power supply domain.
    • A first of the two logic gates is operatively coupled with a first signal.
    • A second of the two logic gates is operatively coupled with a second signal.
    • A second logic block operatively coupled with one of the first and second signals, depending on a state of a control signal.
    • A system component coupled to the second logic block.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 8,190,885 - *"Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions"*

  • Patent Identification: U.S. Patent No. 8,190,885, "Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions", issued May 29, 2012.
  • Technology Synopsis: The patent describes a memory module that integrates non-volatile memory, a security processor, and a near-field communication (NFC) radio frequency component (Compl. ¶24). This creates a secure hardware environment for processing and storing NFC transaction data, with the security processor enabling the creation of memory partitions with specific, hardware-enforced access rights (Compl. ¶25).
  • Asserted Claims: Independent claims 1 and 3 (Compl. ¶55).
  • Accused Features: Branded contactless consumer credit cards, which allegedly contain the integrated secure memory system for handling NFC transactions (Compl. ¶55).

U.S. Patent No. 8,370,543 - *"Busy Detection Logic for Asynchronous Communication Port"*

  • Patent Identification: U.S. Patent No. 8,370,543, "Busy Detection Logic for Asynchronous Communication Port", issued February 5, 2013.
  • Technology Synopsis: The patent addresses the problem of synchronizing access requests between components operating in different clock domains (e.g., a processor and a memory device) (Compl. ¶28). The invention provides a method to achieve this synchronization without the limitations of prior art solutions, which either required control signal pulses to be wider than the clock period or necessitated costly and power-intensive high-speed clocks (Compl. ¶29-30).
  • Asserted Claims: At least independent claim 16 (Compl. ¶65).
  • Accused Features: Branded contactless consumer credit cards, which are alleged to use the claimed synchronization methods for communication between internal components operating at different speeds (Compl. ¶65).

U.S. Patent No. 8,543,628 - *"Method and System of Digital Signal Processing"*

  • Patent Identification: U.S. Patent No. 8,543,628, "Method and System of Digital Signal Processing", issued September 24, 2013.
  • Technology Synopsis: This patent discloses a programmable system on a chip with a dynamically reconfigurable digital filtering system (Compl. ¶32). A microcontroller can load instruction sets that configure a controller and an address-calculation device; these components then select specific filter coefficients that a data path device uses to perform digital signal processing on incoming data, enabling efficient and flexible resource use (Compl. ¶32-33).
  • Asserted Claims: At least independent claim 1 (Compl. ¶75).
  • Accused Features: Branded contactless consumer credit cards, which are alleged to incorporate a reconfigurable digital signal processing system as claimed (Compl. ¶75).

III. The Accused Instrumentality

Product Identification

The Accused Instrumentalities are identified as "branded contactless consumer credit cards" provided and supported by the Defendants (Compl. ¶35, 45, 55, 65, 75).

Functionality and Market Context

The complaint alleges these are standard consumer credit cards enabled with contactless payment technology (Compl. ¶35). The infringement allegations are directed at the underlying semiconductor chips within these cards. The complaint does not provide specific technical details about the operation of these chips. Instead, it asserts on "information and belief" that the use of these cards by Defendants' "partners, clients, customers, and end users" constitutes direct infringement of the patents-in-suit (Compl. ¶35, 37). The complaint implies that for these cards to function as intended for contactless payments, they must necessarily practice the inventions of the asserted patents.

IV. Analysis of Infringement Allegations

The complaint does not include infringement claim charts within its body, instead referencing external exhibits (e.g., Ex. A-1, B-1) that were not provided with the complaint document (Compl. ¶36, 46). Accordingly, a narrative summary of the infringement theories is presented below. No probative visual evidence provided in complaint.

'926 Patent Infringement Allegations

The complaint alleges that Defendants induce infringement of at least claim 1 of the ’926 Patent (Compl. ¶35). The narrative theory suggests that the semiconductor chips within the accused credit cards must contain a reset circuit that practices the claimed invention to ensure reliable operation. This would involve the chip detecting its own operational state (normal vs. abnormal) and selectively generating either a synchronous or an asynchronous reset signal to maintain data integrity or ensure immediate recovery, respectively, as required by the elements of claim 1 (Compl. ¶13-14, 35-36).

'145 Patent Infringement Allegations

The complaint alleges that Defendants induce infringement of at least claim 10 of the ’145 Patent (Compl. ¶45). The infringement theory posits that the chips inside the accused credit cards employ a multiplexing system consistent with claim 10 to manage internal clock signals with low jitter. This system would allegedly feature logic gates arranged in separate power supply domains and controlled by a logic block that ensures only one signal path is active at a time, thereby isolating noise and matching the elements of the asserted system claim (Compl. ¶20, 45-46).

Identified Points of Contention

  • Scope Questions: A primary question for the ’926 patent will be the scope of "operating normally or abnormally." It is an open question whether this phrase is limited to the specific watchdog timer failure mode described in the patent's embodiments or if it can be read more broadly to cover other error states, such as a low voltage condition.
  • Technical Questions: For the ’145 patent, a key technical question is whether the architecture of the accused chips features "separate power supply domain[s]" for its logic gates as understood in the patent. The analysis will question what level of physical and electrical isolation is required to meet this limitation and what evidence the complaint provides that the accused credit cards possess such a structure.

V. Key Claim Terms for Construction

'926 Patent

  • The Term: "operating normally or abnormally" (from Claim 1).
  • Context and Importance: This binary condition is the central trigger for the claimed invention's selective reset functionality. The construction of this term will be critical for determining whether a given operational state of an accused device (e.g., a low-voltage condition, a software error, a hardware fault) falls within the scope of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests that abnormal operation occurs when "a clear signal is not provided from the CPU 11 to the operation detection circuit 21 at the appropriate interval" (’926 Patent, col. 4:38-41). This could be interpreted to encompass any condition that causes the CPU to fail its "heartbeat" or watchdog check.
    • Evidence for a Narrower Interpretation: The patent distinguishes the detection of abnormal CPU operation from the detection of low voltage, which is handled by a separate "low voltage detection circuit 18" (’926 Patent, col. 4:47-52, 7:7-15). This may support an argument that "abnormally" is limited to CPU-specific logical faults and does not include power-related issues, which are detected by a different mechanism.

'145 Patent

  • The Term: "separate power supply domain" (from Claim 10).
  • Context and Importance: The physical and electrical separation of logic components into different power domains is the core mechanism for reducing jitter in the ’145 patent. The viability of the infringement claim will depend heavily on whether the architecture of the accused chips can be shown to meet this structural limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes arranging components within different "power supply 'islands,' each coupled to a different power bus" and notes that "a relatively high substrate resistance also functions to provide isolation" (’145 Patent, col. 3:30-38). This may support a construction that includes various forms of physical and electrical isolation on a single die.
    • Evidence for a Narrower Interpretation: The patent repeatedly emphasizes that a component in a separate power domain is "supplied with its own power bus" and is "physically separated from components arranged in other power domains" (’145 Patent, col. 5:49-53). This could be argued to require a degree of separation beyond mere trace routing, potentially requiring distinct voltage regulators or other substantial divisions.

VI. Other Allegations

Indirect Infringement

The complaint exclusively pleads indirect infringement for all five patents, focusing on inducement under 35 U.S.C. § 271(b) (Compl. ¶35, 45, 65, 75). For the ’885 patent, it additionally pleads contributory infringement under § 271(c) (Compl. ¶55). The factual basis alleged for inducement is that Defendants’ "advertising and distributing the Accused Instrumentalities and providing instruction materials, training, and services" encourages direct infringement by third-party users with the requisite intent (Compl. ¶40, 50, 60, 70, 80).

Willful Infringement

The complaint alleges that Defendants had knowledge of the patents and their infringement "at least as early as the filing of this Complaint" (Compl. ¶38, 48, 58, 68, 78). Accordingly, the prayer for relief seeks a finding of willful infringement based on Defendants' alleged post-suit conduct (Compl. ¶41, 51, 61, 71, 81).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of causation and intent for indirect infringement: The complaint alleges that Defendants, as retailers, induce infringement by their customers and partners. A central question for the court will be whether Plaintiff can produce evidence that Defendants took affirmative acts with the specific intent to encourage third parties to use the internal, chip-level technology of the credit cards in an infringing manner, a potentially challenging link to establish.
  • A second key issue will be one of technical applicability and scope: The case will likely turn on whether the specific, circuit-level solutions described in the patents-in-suit can be shown to read on the integrated circuits found in the accused contactless credit cards. This will raise evidentiary questions about whether the accused products, for example, utilize a "separate power supply domain" for multiplexing ('145 Patent) or a dual-mode synchronous/asynchronous reset circuit ('926 Patent) that matches the claim limitations, or whether they employ alternative, non-infringing technologies to solve similar technical problems.
  • A third dispositive question will concern the damages and apportionment theory: Should infringement be found, the court will face the question of how to value the contribution of these fundamental semiconductor inventions relative to the overall value of a credit card or the financial transactions it facilitates. This raises complex issues of apportionment and the determination of a reasonable royalty for patented features that may constitute a small part of a much larger, multi-featured product.