Induction Devices LLC v. Ross Stores Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Induction Devices LLC (Texas)
  • Defendant: Ross Stores, Inc. (Delaware)
  • Plaintiff’s Counsel: SHEA | BEATY PLLC
• Case Identification: 2:25-cv-00768, E.D. Tex., 08/05/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant, a Delaware corporation, maintains a place of business in Frisco, Texas, and regularly conducts business within the district.
• Core Dispute: Plaintiff alleges that Defendant’s provision and support of branded contactless consumer credit cards indirectly infringes five patents related to fundamental semiconductor circuit technologies.
• Technical Context: The patents-in-suit address various aspects of integrated circuit design, including circuit reset logic, low-jitter signal multiplexing, secure memory for near-field communication (NFC), asynchronous communication ports, and digital signal processing.
• Key Procedural History: The complaint notes that U.S. Patent No. 7,899,145 was previously litigated in the Western District of Texas, but those cases were resolved before any substantive matters were addressed.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - "Circuit for Asynchronously Resetting Synchronous Circuit," issued November 11, 2008

The Invention Explained

• Problem Addressed: The patent describes a problem in synchronous circuits where an abnormal operation (e.g., due to a drop in power supply voltage) requires a reset. However, a standard asynchronous reset can cause the loss of stored data in components like RAM, while a synchronous reset, which preserves data, may not be fast enough to prevent errors during a critical failure (Compl. ¶10; ’926 Patent, col. 1:24-44).
• The Patented Solution: The invention is a reset signal generation circuit that intelligently chooses the type of reset signal to generate. It includes an "operation detection circuit" to determine if a synchronous circuit (like a CPU) is operating normally or abnormally. Based on this detection, a "signal control circuit" generates either a data-preserving synchronous reset signal during normal operation or an immediate asynchronous reset signal during abnormal operation ('926 Patent, Abstract; col. 6:58-7:6).
• Technical Importance: This selective reset capability enhances the overall reliability of a semiconductor device by applying the appropriate reset strategy for different operational states, balancing the need for immediate initialization against the need for data preservation (Compl. ¶11).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 (Compl. ¶32).
• Essential elements of claim 1 include:
  • an operation detection circuit for detecting whether the synchronous circuit is operating normally or abnormally and for generating an operation detection signal;
  • a signal control circuit, connected to the operation detection circuit, for generating the first reset signal based on a system reset signal, the clock signal, and the operation detection signal;
  • wherein the signal control circuit generates the first reset signal that is synchronous to the clock signal in response to the system reset signal when the synchronous circuit is operating normally; and
  • wherein the signal control circuit generates the first reset signal that is asynchronous to the clock signal in response to the system reset signal when the synchronous circuit is operating abnormally.
• The complaint does not explicitly reserve the right to assert dependent claims but makes allegations regarding "at least claim 1" (Compl. ¶32).

U.S. Patent No. 7,899,145 - "Circuit, System, and Method for Multiplexing Signals with Reduced Jitter," issued March 1, 2011

The Invention Explained

• Problem Addressed: In high-speed circuits, when selecting between multiple clock signals using a multiplexer, crosstalk between the signal paths and associated power supply noise can be introduced. This increases "jitter" (timing variations) on the output clock signal, which degrades system performance and reliability (Compl. ¶16; '145 Patent, col. 2:53-63).
• The Patented Solution: The patent proposes a multiplexer design where input signals are fed to separate logic gates. A logic block sends a static control signal to these gates to ensure only one is active at a time, effectively deactivating the path for the unused signal. This method is said to eliminate crosstalk. The invention further teaches arranging these logic gates within separate power supply domains to further isolate them from power supply noise (Compl. ¶17; '145 Patent, col. 3:13-28).
• Technical Importance: By minimizing the injection of crosstalk and power supply noise, this multiplexer design reduces jitter, which is critical for maintaining stable timing in high-frequency digital systems (Compl. ¶15).

Key Claims at a Glance

• The complaint asserts at least independent claim 10 (Compl. ¶42).
• Essential elements of claim 10 include:
  • A system, comprising: a circuit comprising two logic gates and a first logic block and a second logic block, each arranged within a separate power supply domain, wherein:
  • a first of the two logic gates is operatively coupled with a first signal;
  • a second of the two logic gates is operatively coupled with a second signal; and
  • a second logic block operatively coupled with one of the first and second signals, depending on a state of a control signal; and
  • a system component coupled to the second logic block.
• The complaint does not explicitly reserve the right to assert dependent claims but makes allegations regarding "at least claim 10" (Compl. ¶42).

U.S. Patent No. 8,190,885 - "Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions," issued May 29, 2012

• Technology Synopsis: The patent describes a memory module that integrates non-volatile memory, a security processor, and a near-field communication (NFC) component. This architecture creates a secure environment for processing and logging NFC transaction data, with the security processor enforcing access rights to memory partitions (Compl. ¶21, ¶22).
• Asserted Claims: Claims 1 and 3 (Compl. ¶52).
• Accused Features: The technology is allegedly embodied in the semiconductor chips within the accused branded contactless consumer credit cards (Compl. ¶52).

U.S. Patent No. 8,370,543 - "Busy Detection Logic for Asynchronous Communication Port," issued February 5, 2013

• Technology Synopsis: This patent is directed to systems for synchronizing access requests between devices operating in independent clock domains (e.g., a fast processor and a slow memory device). The invention purports to achieve this synchronization without the need for high-speed clocks or specific signal pulse width requirements, thereby reducing circuit complexity and power consumption (Compl. ¶25, ¶26, ¶27).
• Asserted Claims: Claim 16 (indirect infringement) and Claim 1 (direct infringement by end users) (Compl. ¶62, ¶63).
• Accused Features: The technology is allegedly embodied in the semiconductor chips within the accused branded contactless consumer credit cards (Compl. ¶62).

U.S. Patent No. 8,543,628 - "Method and System of Digital Signal Processing," issued September 24, 2013

• Technology Synopsis: The patent describes a programmable system-on-a-chip with a dynamically reconfigurable digital filtering system. An instruction set configures a controller to select filter coefficients, and a data path device uses these coefficients to perform digital signal processing on incoming data, enabling resource-efficient and scalable processing (Compl. ¶29, ¶30).
• Asserted Claims: Claim 1 (Compl. ¶72).
• Accused Features: The technology is allegedly embodied in the semiconductor chips within the accused branded contactless consumer credit cards (Compl. ¶72).

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Instrumentalities" as "branded contactless consumer credit cards" that Defendant provides and supports (Compl. ¶32).

Functionality and Market Context

The complaint alleges that Defendant provides these contactless credit cards to its partners, clients, and customers, who in turn use them in a manner that allegedly constitutes direct infringement of the patents-in-suit (Compl. ¶32, ¶34). The complaint does not provide specific technical details on the internal operation or components of the accused cards. The infringement allegations are directed at the semiconductor chips within these cards, which are alleged to perform the functions described in the patents, such as circuit reset, signal multiplexing, secure NFC communication, asynchronous data handling, and digital signal processing. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references infringement analysis in Exhibits A-1, B-1, C-1, D-1, and E-1, but these exhibits were not filed with the complaint. Therefore, the infringement allegations are summarized below in prose based on the text of the complaint.

’926 Patent Infringement Allegations

The complaint alleges that Defendant induces infringement of at least claim 1 of the ’926 patent (Compl. ¶32). The theory of infringement is that the semiconductor chips within the accused contactless credit cards contain circuits that practice the claimed invention. Specifically, these chips are alleged to include a reset signal generation circuit that detects whether the chip is operating "normally or abnormally" and, based on that determination, selectively generates either a synchronous or an asynchronous reset signal to enhance reliability (Compl. ¶10, ¶33).

’145 Patent Infringement Allegations

The complaint alleges that Defendant induces infringement of at least claim 10 of the ’145 patent (Compl. ¶42). The infringement theory posits that chips inside the accused credit cards contain a system for multiplexing signals that reduces jitter. This system allegedly comprises multiple logic gates and logic blocks arranged within separate power supply domains, where a control signal deactivates one of the inputs to eliminate crosstalk and power supply noise, as recited in the claims (Compl. ¶15, ¶17, ¶43).

Identified Points of Contention

• Evidentiary Questions: The complaint's allegations are made "upon information and belief" and lack specific factual support tying the accused products to the patent claims. A primary point of contention will be what technical evidence is revealed in discovery concerning the actual architecture and operation of the semiconductor chips within the accused credit cards.
• Scope Questions (’926 Patent): A potential dispute may arise over the scope of "operation detection circuit." The patent’s detailed description focuses on a circuit that monitors CPU activity to detect an abnormal state ('926 Patent, col. 4:13-46). The question for the court will be whether this term is limited to such active monitoring or if it can be construed more broadly to cover simpler functions like a standard low-voltage detection circuit.
• Technical Questions (’145 Patent): The infringement allegation for the ’145 patent hinges on the physical layout of the accused chips. A key technical question will be whether the logic components in the accused chips are in fact arranged in "separate power supply domain[s]" as required by claim 10. Proving this limitation is met may require detailed analysis of the chip's physical design.

V. Key Claim Terms for Construction

For the ’926 Patent

• The Term: "operation detection circuit" (Claim 1)
• Context and Importance: This term is central to defining how the invention decides between a synchronous and asynchronous reset. Plaintiff may seek a broad construction covering any circuit that detects a non-normal condition, while Defendant may argue for a narrower construction limited to the specific embodiments described in the patent. Practitioners may focus on this term because its construction could determine whether a standard low-voltage detector found in many commercial chips meets the claim limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The plain language of the claim requires a circuit "for detecting whether the synchronous circuit is operating normally or abnormally," which does not specify the method of detection (’926 Patent, col. 13:8-11).
  • Evidence for a Narrower Interpretation: The only embodiment detailed in the specification describes a circuit that monitors a CPU by using an up-counter that is periodically cleared by the CPU; an abnormal state is detected if the counter exceeds a predetermined value before being cleared (’926 Patent, col. 4:13-46). This specific disclosure may be used to argue for a more limited scope.

For the ’145 Patent

• The Term: "each arranged within a separate power supply domain" (Claim 10)
• Context and Importance: This limitation is a core inventive concept for isolating noise. The infringement dispute will likely turn on what degree of physical and electrical separation is required to constitute a "separate power supply domain" on a semiconductor chip.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself is not explicitly defined, which may support an argument that any distinct power routing to the different logic gates satisfies the limitation.
  • Evidence for a Narrower Interpretation: The specification describes arranging logic gates within different power supply "islands," each coupled to a different power bus, and mentions the use of "supply guard rings for further isolation" (’145 Patent, col. 3:30-33; col. 6:58-60). This language suggests a more robust and deliberate physical separation than merely separate wiring traces.

VI. Other Allegations

Indirect Infringement

The complaint pleads exclusively for indirect infringement by way of inducement under 35 U.S.C. § 271(b) for all five patents-in-suit. The basis for inducement is Defendant's alleged "provision and support of branded contactless consumer credit cards" and associated "instruction materials, training, and services," which allegedly cause end users to directly infringe the patents (Compl. ¶32, ¶36, ¶37).

Willful Infringement

Plaintiff alleges willful infringement for all asserted patents. The allegation of knowledge is based entirely on the filing of the complaint, with Plaintiff asserting that Defendant's inducement has been willful "since at least the time Defendant received notice" via the lawsuit (Compl. ¶36, ¶38, ¶46, ¶48).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of technical evidence: can Plaintiff, through discovery, produce concrete evidence showing that the internal architecture of the semiconductor chips in the accused contactless credit cards practices the specific technologies claimed in the five asserted patents? The complaint currently relies on "information and belief" without offering public-facing proof.
• The case will also turn on a question of claim construction and scope: will the key limitations of the asserted claims—such as the "operation detection circuit" of the ’926 patent and the "separate power supply domain" of the ’145 patent—be interpreted broadly enough to read on the likely mass-produced, cost-optimized designs of the accused products, or will they be narrowed to the specific, more complex embodiments detailed in the patent specifications?
• A third key question relates to inducement: assuming direct infringement by end users is established, can Plaintiff prove that Defendant, by merely providing and supporting contactless credit cards, possessed the specific intent required to encourage its customers to infringe the patents-in-suit?