DCT

2:25-cv-00777

Induction Devices LLC v. IKEA US Retail LLC

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00777, E.D. Tex., 01/14/2026
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains a place of business in the district and conducts regular business there.
  • Core Dispute: Plaintiff alleges that Defendant’s branded contactless consumer credit cards induce infringement of five patents related to semiconductor circuit design, secure memory systems, and signal processing.
  • Technical Context: The patents-in-suit relate to foundational semiconductor technologies for enhancing circuit reliability, reducing signal jitter, enabling secure transactions, and managing data across different clock domains.
  • Key Procedural History: The complaint notes that U.S. Patent No. 7,899,145 was previously litigated in the Western District of Texas, but those cases were resolved before any substantive matters were addressed.

Case Timeline

Date Event
2005-09-02 U.S. Patent No. 7,899,145 Priority Date
2006-01-26 U.S. Patent No. 7,449,926 Priority Date
2006-12-21 U.S. Patent No. 8,190,885 Priority Date
2007-03-09 U.S. Patent No. 8,370,543 Priority Date
2007-04-17 U.S. Patent No. 8,543,628 Priority Date
2008-11-11 U.S. Patent No. 7,449,926 Issued
2011-03-01 U.S. Patent No. 7,899,145 Issued
2012-05-29 U.S. Patent No. 8,190,885 Issued
2013-02-05 U.S. Patent No. 8,370,543 Issued
2013-09-24 U.S. Patent No. 8,543,628 Issued
2026-01-14 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - *"Circuit for Asynchronously Resetting Synchronous Circuit"* (Issued Nov. 11, 2008)

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of reliably resetting a synchronous circuit, such as a microprocessor system. An asynchronous reset, while immediate, can cause data loss in memory components like RAM, whereas a synchronous reset preserves data but may fail if the circuit is already operating abnormally and its clock signal is unstable (Compl. ¶10; ’926 Patent, col. 1:35-46).
  • The Patented Solution: The invention provides a reset signal generation circuit that detects the operational state of the synchronous circuit (e.g., a CPU). If the circuit is operating normally, the invention generates a reset signal that is synchronous to the system clock, preserving data. If the circuit is operating abnormally (e.g., has failed to perform a periodic check-in), it generates an asynchronous reset signal to ensure an immediate and complete initialization (Compl. ¶11; ’926 Patent, col. 2:1-7). The circuit can also select between synchronous and asynchronous resets based on the power supply voltage level (Compl. ¶12; ’926 Patent, col. 7:7-15).
  • Technical Importance: This dual-mode approach enhances overall circuit reliability by providing a mechanism that ensures both data integrity during normal operation and guaranteed recovery from fault states (Compl. ¶11).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and reserves the right to assert additional claims (Compl. ¶33-34).
  • Independent Claim 1 requires:
    • An operation detection circuit for detecting whether a synchronous circuit is operating normally or abnormally and generating a corresponding operation detection signal.
    • A signal control circuit that receives the operation detection signal and a system reset signal.
    • The signal control circuit generates a first reset signal that is synchronous to the clock signal when the circuit is operating normally.
    • The signal control circuit generates a first reset signal that is asynchronous to the clock signal when the circuit is operating abnormally.

U.S. Patent No. 7,899,145 - *"Circuit, System, and Method for Multiplexing Signals with Reduced Jitter"* (Issued Mar. 1, 2011)

The Invention Explained

  • Problem Addressed: In high-speed electronics, selecting between multiple clock signals using a conventional multiplexer introduces electrical noise (crosstalk and power supply noise) into the signal path. This noise creates timing variations known as "jitter," which can degrade system performance and cause errors (Compl. ¶16; ’145 Patent, col. 2:53-63).
  • The Patented Solution: The patent describes a multiplexer circuit designed to minimize jitter. The solution involves physically and electrically separating the logic gates that handle the different input signals into distinct "power supply domains." A logic block deactivates one of the signal paths by supplying a static control signal, ensuring that only one active signal is presented to the downstream logic at any time. This isolation prevents the signals from interfering with each other, thereby reducing crosstalk and noise (Compl. ¶17; ’145 Patent, col. 3:13-28).
  • Technical Importance: This architecture provides a cleaner, more stable output signal when switching between clock sources, which is critical for maintaining timing integrity in high-performance synchronous systems (Compl. ¶15).

Key Claims at a Glance

  • The complaint asserts independent claim 10 and reserves the right to assert additional claims (Compl. ¶43-44).
  • Independent Claim 10 requires a system comprising:
    • A circuit with two logic gates, a first logic block, and a second logic block, where each is arranged within a separate power supply domain.
    • A first logic gate coupled to a first signal and a second logic gate coupled to a second signal.
    • A second logic block coupled to receive only one of the first or second signals, based on a control signal's state.
    • A system component coupled to the output of the second logic block.

U.S. Patent No. 8,190,885 - *"Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions"* (Issued May 29, 2012)

  • Technology Synopsis: The patent describes a memory module that enhances security for Near Field Communication (NFC) transactions. It achieves this by tightly integrating non-volatile memory, a security processor, and an NFC radio component into a single secure execution environment, allowing for secure data processing, partitioned memory with individualized access rights, and secure transaction logging (Compl. ¶21-22).
  • Asserted Claims: Independent claims 1 and 3 (Compl. ¶53).
  • Accused Features: Branded contactless consumer credit cards, which allegedly contain the claimed integrated secure memory sub-system (Compl. ¶53).

U.S. Patent No. 8,370,543 - *"Busy Detection Logic for Asynchronous Communication Port"* (Issued February 5, 2013)

  • Technology Synopsis: The patent addresses the technical problem of synchronizing access to a shared resource (e.g., memory) between two components operating in different, independent clock domains. The invention provides a system that manages this synchronization without requiring high-speed clocks or imposing minimum pulse-width requirements on control signals, thereby reducing circuit complexity and power consumption (Compl. ¶25-27).
  • Asserted Claims: Independent claim 16 (Compl. ¶63, ¶70).
  • Accused Features: Branded contactless consumer credit cards, which allegedly use the claimed logic for communication between different internal components (Compl. ¶63).

U.S. Patent No. 8,543,628 - *"Method and System of Digital Signal Processing"* (Issued September 24, 2013)

  • Technology Synopsis: The patent is directed to a dynamically reconfigurable digital signal processing system on a chip. A microcontroller provides instructions to configure a controller and an address-calculation device, which in turn select filter coefficients for a data path device to use when processing incoming digital data. This architecture allows for resource-efficient and adaptable signal filtering (Compl. ¶30-31).
  • Asserted Claims: Independent claim 1 (Compl. ¶73).
  • Accused Features: Branded contactless consumer credit cards, which allegedly incorporate the claimed programmable digital signal processing system (Compl. ¶73).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies the accused instrumentalities as "branded contactless consumer credit cards" that Defendant provides and supports (Compl. ¶33).
  • Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the technical functionality of the accused credit cards. It alleges that the cards are marketed and used by Defendant's partners, clients, and customers nationwide (Compl. ¶35). The infringement theory is based on the allegation that the semiconductor chips within these cards contain circuitry that practices the claimed inventions (Compl. ¶34, ¶44, ¶54, ¶64, ¶74).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits for each asserted patent (Exhibits A-1, B-1, C-1, D-1, E-1) but does not attach them (Compl. ¶34, ¶44, ¶54, ¶64, ¶74). In the absence of these exhibits, the infringement allegations are summarized below in prose. No probative visual evidence provided in complaint.

  • U.S. Patent No. 7,449,926 (Claim 1): The complaint alleges that the accused credit cards contain a reset signal generation circuit that infringes claim 1. The narrative theory is that this circuit detects the operational state of a synchronous circuit within the card's chip and, based on that state, selectively generates either a synchronous or an asynchronous reset signal (Compl. ¶34).

    • Identified Points of Contention: A central question will be evidentiary: do the integrated circuits within the accused credit cards contain a reset circuit that performs the specific function of detecting a "normal or abnormal" operating state and switching its reset signal timing accordingly? The complaint does not specify what feature of the accused cards is alleged to constitute this "operation detection circuit."

  • U.S. Patent No. 7,899,145 (Claim 10): The complaint alleges that the accused credit cards contain a system for multiplexing signals that infringes claim 10. The narrative theory is that the cards' internal circuitry includes logic gates and logic blocks arranged in separate power supply domains to reduce signal jitter, as claimed (Compl. ¶44).

    • Identified Points of Contention: The analysis will likely focus on both claim construction and evidence. A key question of scope will be the definition of a "separate power supply domain." An evidentiary question will be whether the circuitry in the accused cards, in fact, implements such a physically and electrically distinct architecture for its signal multiplexing components.

V. Key Claim Terms for Construction

  • Term from ’926 Patent: "operating normally or abnormally"

    • Context and Importance: This phrase is the trigger for the claimed invention's core functionality of selecting between two different types of reset signals. The definition of what constitutes "abnormal" operation will be central to determining whether the accused devices perform the claimed function.
    • Intrinsic Evidence for a Broader Interpretation: The specification suggests that abnormal operation occurs when "a clear signal is not provided from the CPU 11... at the appropriate interval," which could be argued to encompass any failure of a periodic "heartbeat" or check-in signal (’926 Patent, col. 4:38-41).
    • Intrinsic Evidence for a Narrower Interpretation: The primary embodiment describes the detection circuit as an up-counter that is periodically reset by the CPU; "abnormal" operation is defined as the counter exceeding a predetermined value. This could support an argument that the term is limited to such a counter-based fault detection mechanism (’926 Patent, col. 4:15-34).

  • Term from ’145 Patent: "separate power supply domain"

    • Context and Importance: This term defines the key structural element of the claimed multiplexer, which is intended to provide electrical isolation to reduce noise. The infringement analysis for claim 10 will depend entirely on whether the components in the accused products are arranged in what the court construes to be "separate" domains.
    • Intrinsic Evidence for a Broader Interpretation: The specification refers to arranging logic gates within different power supply "islands,' each coupled to a different power bus," which might support a broader reading that any distinct power trace constitutes a separate domain (’145 Patent, col. 3:32-34).
    • Intrinsic Evidence for a Narrower Interpretation: The specification's emphasis on isolation—noting that "a relatively high substrate resistance also functions to provide isolation"—could support a narrower construction requiring a specific degree of electrical or physical separation, such as through guard rings or distinct voltage regulators, beyond merely using different traces (’145 Patent, col. 3:36-38).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for all five patents. The basis for inducement is Defendant's alleged "advertising and distributing the Accused Instrumentalities and providing instruction materials, training, and services" for them, which allegedly aid and abet direct infringement by end users and partners (Compl. ¶38, ¶48, ¶58, ¶68, ¶78).
  • Willful Infringement: Willfulness is alleged based on Defendant's knowledge of the patents and the alleged infringement "since at least the filing of this Complaint" (Compl. ¶39, ¶49, ¶59, ¶69, ¶79). This constitutes an allegation of post-suit willfulness.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Evidentiary Proof: A central issue for the plaintiff will be an evidentiary one. Can discovery demonstrate that the specific and complex circuit architectures claimed across the five patents—such as dual-mode reset logic ('926), multi-power-domain multiplexers ('145), and integrated secure NFC subsystems (’885)—are actually present and operative within the commodity semiconductor chips used in Defendant's branded credit cards? The complaint itself offers no specific technical evidence.

  2. Claim Scope: The case will likely involve significant disputes over claim construction. A core issue will be one of definitional scope: what level of circuit monitoring constitutes "detecting whether the synchronous circuit is operating normally or abnormally" under the ’926 Patent, and what degree of electrical and physical isolation is required for components to be in "separate power supply domains" as required by the ’145 Patent?

  3. Proof of Intent for Inducement: As the case is pleaded entirely on a theory of induced infringement, a key legal question will be one of intent. Can Plaintiff prove that Defendant, by merely branding and distributing contactless credit cards, possessed the specific intent to encourage its customers to infringe the asserted patents, particularly where the allegation of knowledge is based on the filing of the complaint itself?