DCT
2:25-cv-00825
Empire Technology Development LLC v. Texas Instruments Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Empire Technology Development LLC (Delaware)
- Defendant: Texas Instruments Incorporated (Delaware)
- Plaintiff’s Counsel: Capshaw DeRieux, LLP; Milbank LLP
- Case Identification: 2:25-cv-00825, E.D. Tex., 08/20/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant has committed acts of infringement and maintains regular and established places of business within the district.
- Core Dispute: Plaintiff alleges that Defendant’s System-on-Chip (SoC) products infringe two patents related to methods for efficiently routing data across on-chip networks and for managing memory requests in multicore processor systems.
- Technical Context: The technologies at issue aim to improve the performance and efficiency of multicore processors, which are critical components in computationally intensive applications such as automotive infotainment systems, mobile computing, and artificial intelligence.
- Key Procedural History: The complaint alleges that Defendant has had actual knowledge of the patents-in-suit since at least February 2020, following communications from Plaintiff’s agent regarding a patent portfolio offered for sale that included the asserted patents.
Case Timeline
| Date | Event |
|---|---|
| 2009-05-21 | U.S. Patent No. 8,180,963 Priority Date |
| 2009-08-20 | U.S. Patent No. 9,189,448 Priority Date |
| 2012-05-15 | U.S. Patent No. 8,180,963 Issue Date |
| 2015-11-17 | U.S. Patent No. 9,189,448 Issue Date |
| c. August 2016 | Accused DRA78x Series Product Launch |
| 2020-02-25 | Plaintiff allegedly notified Defendant of patents-in-suit |
| 2025-08-20 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,189,448 - "ROUTING IMAGE DATA ACROSS ON-CHIP NETWORKS" (Issued Nov. 17, 2015)
The Invention Explained
- Problem Addressed: The patent’s background section describes the challenge that processing state-of-the-art computer simulation and animation often requires computational resources that exceed the capabilities of available computing power, making improvements in processing efficiency desirable (’448 Patent, col. 1:11-23).
- The Patented Solution: The invention proposes a method for distributing computational tasks across a multi-core chip more efficiently. It involves taking image data, spatially transforming it into a "reference space" (e.g., the real-world physical space the image represents), and then creating data samples tagged with coordinate values from that reference space. These tagged samples are then "self-routed" through an on-chip network of switches to specific processors that are pre-assigned to handle computations for different regions of that reference space (’448 Patent, Abstract; col. 4:1-10).
- Technical Importance: This approach aims to streamline the assignment of data processing tasks in parallel computing environments, which is relevant for applications like virtual reality, automotive navigation displays, and scientific simulations (Compl. ¶17).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶28).
- Claim 1 recites an apparatus comprising:
- A plurality of processors;
- A plurality of switches arranged in a network;
- Wherein the network routes data samples based on tags, and each tag includes a "reference-space coordinate value" from a space that is spatially transformed from an image space;
- Wherein each processor is assigned to a portion of the reference space; and
- Wherein each data sample is "self-routed" through the network using switches programmed with distribution rules that map the coordinate values to the processors, and the network can modify this routing based on "time-dependent changes."
U.S. Patent No. 8,180,963 - "HIERARCHICAL READ-COMBINING LOCAL MEMORIES" (Issued May 15, 2012)
The Invention Explained
- Problem Addressed: The patent addresses a common bottleneck in multicore processors where multiple processing cores simultaneously request the same piece of data from memory. The patent notes that there is often insufficient bandwidth to fulfill all of these duplicative requests rapidly, leading to inefficiency (’963 Patent, col. 1:8-14).
- The Patented Solution: The patent describes a hierarchical memory system where memory controllers can "selectively hold" a data request for a period of time. This pause allows the controller to wait and see if other requests for the same data arrive from other cores. If they do, the controller can combine these multiple requests into a single "read-combined" request that is then sent to the next level of the memory hierarchy. This consolidation reduces memory bus traffic and increases overall system efficiency (’963 Patent, Abstract; col. 4:15-21; Fig. 2).
- Technical Importance: By reducing redundant memory requests, this technology seeks to improve performance in multicore systems, which is foundational for modern computing in areas from personal devices to network processing (Compl. ¶¶ 19-20).
Key Claims at a Glance
- The complaint asserts at least independent claims 1 and/or 20 (Compl. ¶72).
- Claim 1 recites a system comprising:
- A multicore processor coupled to a memory controller;
- A hierarchy of memory levels;
- A plurality of memory controllers;
- Wherein each memory controller is configured to receive data requests, "selectively hold a request... for an undetermined amount of time," and combine multiple requests for the same data into a single request for a higher level in the hierarchy.
- Claim 20 is nearly identical to Claim 1, but requires the memory controller to "selectively hold a first request... for a predetermined amount of time."
III. The Accused Instrumentality
Product Identification
- The complaint identifies numerous Texas Instruments SoC products. The lead accused products for the ’448 Patent are the DRA78x series of SoCs for automotive infotainment (Compl. ¶24). The lead accused products for the ’963 Patent are the 66AK2G1x series of multicore DSP+Arm SoCs (Compl. ¶69).
Functionality and Market Context
- The DRA78x series are described as SoCs featuring video and image processing capabilities, including a "Dual Arm Cortex-M4 Image Processing Unit (IPU)" and multiple digital signal processors (DSPs) (Compl. ¶¶ 34, 37). The complaint focuses on a "line multiplexing" feature that allegedly uses "Metadata tag[s]" to interleave video data from multiple camera sources (Compl. ¶43).
- The 66AK2G1x series are described as highly integrated SoCs for applications requiring both DSP and Arm performance (Compl. ¶79). These chips contain an Arm Cortex-A15 core, a C66x DSP core, and a memory subsystem with multiple levels of cache and multiple memory controllers, including a Multicore Shared Memory Controller (MSMC) designed to manage traffic between the cores and shared memory (Compl. ¶¶ 84, 90, 94). The complaint alleges these products are used in designs that benefit from hierarchical memory management (Compl. ¶80).
IV. Analysis of Infringement Allegations
’448 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| An apparatus that is arranged to process image data... | The DRA78x series are SoCs described as having "video and image processing support." | ¶33, ¶34 | col. 1:6-10 |
| a plurality of processors; and | The DRA78x series allegedly contains an Image Processing Unit with two Arm Cortex-M4 cores and two DSP subsystems. | ¶37 | col. 2:37-39 |
| a plurality of switches arranged in a network, | The "interconnect" shown in the product block diagram is alleged to be a network of switches. A block diagram of the DRA78x is provided as visual evidence (Compl. p. 11, Fig. 1-1). | ¶39 | col. 2:64-67 |
| wherein the network is arranged to use the switches to selectively route data samples... based on tags associated with the data samples, | The "line multiplexing" feature allegedly uses "Metadata tag[s]" to interleave and route video data from different camera sources. | ¶42, ¶43 | col. 2:13-18 |
| wherein each tag includes at least one reference-space coordinate value of a reference space that is spatially transformed from an image space... | The complaint alleges the metadata tags identify the line in a camera frame, which constitutes a reference-space coordinate value spatially transformed from the captured image. | ¶44 | col. 4:32-37 |
| wherein each data sample is self-routed through the network by use of a self-routing process... and wherein the network is arranged to use the switches to modify routing... based on time-dependent changes... | The complaint alleges that interprocessor communication is managed by programmable distribution rules and that a change in a video timing signal (SAV codeword) causes "retagging," which modifies routing based on changed circumstances. | ¶56, ¶57 | col. 4:1-24 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the "Metadata tag" used for video "line multiplexing" in the accused products can be construed as a tag containing a "reference-space coordinate value" used for routing computational workload, as the patent describes. The analysis may explore whether this is a functional mapping or an application of terms to a dissimilar technology.
- Technical Questions: What evidence does the complaint provide that the accused product’s network modifies routing based on "time-dependent changes" in the manner claimed? The complaint's theory connecting this limitation to a change in a "Start of Active Video" codeword may be a point of dispute regarding the technical mechanism of operation (Compl. ¶57).
’963 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A system for hierarchical read-combining memory comprising: | The 66AK2G1x product series are described as products sold by TI with hierarchical read-combining memory systems. | ¶78 | col. 2:5-8 |
| a multicore processor operably coupled to a memory controller; | The accused SoCs contain an Arm Cortex-A15 core and a C66x DSP core coupled to a memory subsystem with a Multicore Shared Memory Controller (MSMC). | ¶83, ¶84 | col. 2:16-23 |
| a hierarchy of one or more levels of memory; and | The processor cores allegedly contain L1 and L2 memory, which, along with external memory, form a hierarchy. The complaint provides a diagram illustrating memory hierarchies within the C66x DSP core (Compl. p. 27). | ¶90 | col. 2:51-55 |
| a plurality of memory controllers... | The accused SoCs allegedly contain multiple memory controllers, including the MSMC, DDR EMIF, GPMC, and others. | ¶93, ¶94 | col. 4:56-58 |
| wherein each... is configured to... selectively hold a request... for an undetermined amount of time, and selectively combine a plurality of requests for the same data into a single read-combined data request... | The complaint alleges that requests are held via mechanisms like hardware semaphores or are managed by starvation-bound registers, and that TI's programming guides instruct users on combining tasks. A functional block diagram of the MSMC is provided to show it receives data from core processors (Compl. p. 30, Fig. 7-2). | ¶96, ¶102, ¶109, ¶112 | col. 4:15-21 |
- Identified Points of Contention:
- Scope Questions: The dispute may turn on the meaning of "selectively hold a request... for an undetermined amount of time." The question will be whether inherent hardware latencies, bus arbitration schemes, or semaphore-based locks in the accused products meet the claimed function, which appears to describe an intentional, opportunistic pause for the purpose of combining requests.
- Technical Questions: Does the complaint offer sufficient evidence that the accused MSMC or other controllers actually combine multiple, identical read requests into a single outgoing request? The complaint points to programming guides for "combining tasks" (Compl. ¶112), which may or may not map directly to the specific "read-combined data request" recited in the claim.
V. Key Claim Terms for Construction
’448 Patent
- The Term: "self-routed"
- Context and Importance: This term is central to how the patented system differs from traditional architectures. The infringement analysis depends on whether the accused network, which allegedly uses "distribution rules," performs a process that can be defined as "self-routing."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification suggests the process is distinguished by not requiring "a separate program to route data samples" or requiring "individual cores... to fetch each datum from a shared memory" (’448 Patent, col. 4:5-8). This could support a broad definition covering any decentralized routing logic embedded in the network fabric.
- Evidence for a Narrower Interpretation: The patent provides a specific example where a switch uses X and Y coordinates to make simple directional routing decisions (’448 Patent, col. 4:10-19). This embodiment could be cited to argue for a narrower construction limited to direct, coordinate-based routing by individual switches.
’963 Patent
- The Term: "selectively hold a request... for an undetermined amount of time" (Claim 1)
- Context and Importance: This phrase distinguishes Claim 1 from Claim 20 (which recites "predetermined") and is the core mechanism of the invention. The viability of the infringement allegation against Claim 1 hinges on whether the accused devices' operations fall within the scope of this term.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification explains that a memory controller "may hold the data request for some period of time, in order to wait for additional requests for the same chunk of data" (’963 Patent, col. 4:17-20). The phrase "some period of time" and the claim's use of "undetermined" could support an interpretation that covers any non-fixed delay where combining is possible.
- Evidence for a Narrower Interpretation: The specification lists several factors that can influence the hold duration, such as bus availability or the number of core requests exceeding a threshold (’963 Patent, col. 4:35-50). A party could argue that because the hold time is governed by such hardware states, it is algorithmically determined, not "undetermined." The explicit differentiation from "predetermined" in Claim 20 suggests "undetermined" must have a distinct, non-trivial meaning.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement of infringement for both patents, asserting that Defendant provides customers with technical documentation, product manuals, and development tools that instruct them to use the accused SoCs in an infringing manner (Compl. ¶29, ¶73). The complaint also alleges contributory infringement, stating the accused products are a material part of the patented inventions and have no substantial non-infringing use (Compl. ¶30, ¶74).
- Willful Infringement: Willfulness allegations for both patents are based on alleged pre-suit knowledge. The complaint claims that Defendant knew of the patents since at least February 25, 2020, as a result of communications from Plaintiff's agent concerning a patent portfolio offered for sale (Compl. ¶58, ¶113).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue for the ’448 patent will be one of technical analogy: does the accused SoCs' use of "metadata tags" for synchronizing video streams in a "line multiplexing" system constitute the claimed invention of "self-routing" data samples based on "reference-space coordinates" to distribute computational workload? The case may depend on whether Plaintiff can prove these are functionally equivalent processes rather than distinct technologies.
- The dispute over the ’963 patent will likely be a question of definitional scope: can standard processor operations—such as memory access delays caused by bus arbitration, starvation-avoidance timers, or semaphore locks—be construed as "selectively hold[ing] a request... for an undetermined amount of time" for the specific purpose of "read-combin[ing]" requests, as required by Claim 1?
- A key evidentiary question for both asserted patents will be one of operational proof: the complaint's infringement theories are based on interpretations of high-level datasheets and block diagrams. The outcome may depend on whether Plaintiff can produce concrete evidence demonstrating that the accused SoCs internally operate in the specific manner required by the claims, moving beyond architectural descriptions to proven functional behavior.