DCT
2:25-cv-00951
Wecrevention Inc v. Apple Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: WeCrevention, Inc. (Texas)
- Defendant: Apple Inc. (California)
- Plaintiff’s Counsel: Fabricant LLP
- Case Identification: 2:25-cv-00951, E.D. Tex., 09/16/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains regular and established places of business in the district through its "Apple Shops" located within Best Buy stores and "Apple Experience" shops within Target stores. The complaint asserts these locations are staffed by Apple employees, controlled by Apple, and held out to the public as Apple's places of business.
- Core Dispute: Plaintiff alleges that Defendant’s iPhones, MacBooks, and iPads containing LPDDR5 DRAM infringe five patents related to high-speed memory module architecture, DRAM power management, and data transfer protocols.
- Technical Context: The technology at issue involves the architecture of memory systems in high-performance computing devices, focusing on methods to increase data transfer efficiency and reduce power consumption in mobile electronics.
- Key Procedural History: The complaint does not reference any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history concerning the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2011-10-11 | Earliest Priority Date for ’942 and ’834 Patents |
| 2012-07-17 | Earliest Priority Date for ’017, ’098, and ’652 Patents |
| 2015-10-20 | ’942 Patent Issued |
| 2015-12-01 | ’834 Patent Issued |
| 2019-09-01 | Alleged Earliest Accused Product Launch (LPDDR5 products) |
| 2021-05-04 | ’017 Patent Issued |
| 2024-02-06 | ’098 Patent Issued |
| 2024-11-26 | ’652 Patent Issued |
| 2025-09-16 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,201,834 - "Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module"
The Invention Explained
- Problem Addressed: The patent’s background section describes the technical challenges that arise when integrating memory and logic units that are manufactured using different and often incompatible semiconductor process generations, which can lead to poor heat dissipation, high power consumption, and noise interference (U.S. Patent No. 9,201,834, col. 1:35-44).
- The Patented Solution: The invention proposes an electronic device architecture featuring separate memory and logic units connected by programmable data buses. As illustrated in Figure 13, a "logic unit" acts as an intermediary between a "memory cell array group" and an "ASIC processor," using a first and second transmission bus whose characteristics (e.g., data rate, signal swing) can be reconfigured. This allows for optimized communication between components manufactured with different processes (’834 Patent, Abstract; col. 2:21-34; Fig. 13).
- Technical Importance: This reconfigurable architecture provides design flexibility, allowing system builders to use memory and logic components from optimal, distinct manufacturing processes without sacrificing data transfer efficiency or power performance (’834 Patent, col. 2:35-42).
Key Claims at a Glance
- The complaint asserts independent claim 21 (Compl. ¶35).
- Essential elements of claim 21 include:
- An application-specific integrated circuit (ASIC) processor;
- A memory cell array group comprising multiple memory cell array ICs;
- A first transmission bus coupled to the memory group, having a first programmable data rate and signal swing corresponding to firmware or software in the ASIC processor;
- A logic unit coupled to the first transmission bus for accessing the memory group; and
- A second transmission bus between the logic unit and the ASIC processor, having a second programmable data rate and signal swing associated with the firmware or software in the ASIC processor.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 10,998,017 - "Dynamic random access memory applied to an embedded display port"
The Invention Explained
- Problem Addressed: The patent addresses power consumption in mobile device displays that use a panel self-refresh (PSR) feature. While PSR allows the main graphics processing unit (GPU) to power down, it requires the display’s timing controller to use an on-board frame buffer (DRAM), which increases the timing controller's own power consumption (’017 Patent, col. 1:36-61).
- The Patented Solution: The invention claims a DRAM architecture where the "DRAM core cell" and a "peripheral circuit" are designed to operate at voltages lower than the 1.1V minimum specified by some industry standards. This configuration, shown conceptually in Figure 1, reduces the DRAM's overall power consumption, making it more suitable for use as a frame buffer in power-sensitive applications like eDP with PSR (’017 Patent, Abstract; col. 2:19-34; Fig. 1).
- Technical Importance: This low-voltage DRAM design helps resolve the power trade-off inherent in advanced display features, enabling longer battery life in portable devices by reducing the power penalty associated with the frame buffer (’017 Patent, col. 2:28-34).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶55).
- Essential elements of claim 1 include:
- A DRAM core cell supplied with a first voltage lower than 1.1V;
- A peripheral circuit electrically connected to the DRAM core cell, supplied with a second voltage lower than 1.1V;
- The DRAM core cell and peripheral circuit are formed on a single chip, with the peripheral circuit being external to the DRAM core cell; and
- The first and second voltages are capable of making the DRAM be applied to an embedded display port (eDP).
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 11,894,098 - "Dynamic random access memory applied to an embedded display port"
- Technology Synopsis: This patent, related to the ’017 Patent, describes a low-power DRAM architecture. It claims a DRAM where the core cell and a peripheral circuit are on a single chip, operate at voltages below 1.1V, and importantly, the first voltage supplied to the core is different from the second voltage supplied to the peripheral circuit, further enabling power optimization (’098 Patent, Abstract; Compl. ¶69).
- Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶69).
- Accused Features: The complaint accuses the LPDDR5 DRAM in Apple’s products, which allegedly uses distinct low-voltage rails (VDD2H and VDD2L) to supply different voltages to the DRAM core and peripheral circuits during low-power operation modes (Compl. ¶¶71-74).
U.S. Patent No. 12,154,652 - "Dynamic random access memory applied to an embedded display port"
- Technology Synopsis: This patent also concerns low-voltage DRAM design. The invention is a DRAM comprising a core cell and an input/output (I/O) circuit on a single chip. The core cell operates at a first voltage and the I/O circuit operates at a third voltage, with both voltages being below 1.1V and different from each other, to reduce power consumption (’652 Patent, Abstract; Compl. ¶82).
- Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶82).
- Accused Features: The LPDDR5 DRAM in the accused products is alleged to infringe by using separate low-voltage power rails for the DRAM core (e.g., VDD2H/VDD2L) and for the I/O circuit (VDDQ), where these voltages are below 1.1V and distinct from one another (Compl. ¶¶84-88).
U.S. Patent No. 9,164,942 - "High speed memory chip module and electronics system device with a high speed memory chip module"
- Technology Synopsis: This patent, related to the ’834 Patent, describes a high-speed memory system architecture. It claims a device where a logic unit accesses multiple memory ICs via a wide first transmission bus, converts this first set of parallel data into a second set of parallel data with a different bit width, and transmits it to an ASIC processor over a second transmission bus, facilitating efficient communication between disparate components (’942 Patent, Abstract; Compl. ¶96).
- Asserted Claims: The complaint asserts independent claim 19 (Compl. ¶96).
- Accused Features: The complaint accuses the integrated memory controller (IMC) within Apple’s A16 chip. The IMC allegedly accesses the LPDDR5 DRAM via a wide bus (e.g., x64) and converts the data for transmission to the ASIC processor cores over an internal interconnect (e.g., AXI) with a different data width (Compl. ¶¶101-105).
III. The Accused Instrumentality
Product Identification
- The complaint identifies all versions and variants of Apple products including LPDDR5 DRAM since September 2019, including the iPhone 14 and later, certain MacBook models, and certain iPad models. The iPhone 14 Pro, containing an A16 Bionic System-on-Chip ("A16") and 6 GB of LPDDR5 DRAM, is identified as a representative accused product (Compl. ¶29, ¶36).
Functionality and Market Context
- The accused functionality centers on the architecture of the A16 chip, specifically its integrated memory controller (IMC), its interface with the LPDDR5 DRAM, and its power management systems (Compl. ¶39, ¶41). The complaint alleges the A16's IMC manages data transfer between the DRAM and the chip's processor cores and utilizes Dynamic Voltage and Frequency Scaling (DVFS) to adjust operating voltages and frequencies, which allegedly practices the inventions of the patents-in-suit (Compl. ¶40, ¶57). An annotated die shot from a third-party analysis is provided to show the alleged location of the IMC relative to the processor cores and memory interface (Compl. p. 22).
IV. Analysis of Infringement Allegations
9,201,834 Patent Infringement Allegations
| Claim Element (from Independent Claim 21) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an application-specific integrated circuit (ASIC) processor | The Apple A16 Bionic chip, which includes high-performance and energy-efficient processor cores. | ¶37 | col. 4:6-8 |
| a type of memory cell array group, wherein the type of memory cell array group comprises multiple memory cell array ICs | The LPDDR5 DRAM package coupled to the A16, which is comprised of multiple memory cell array ICs. | ¶38 | col. 3:40-43 |
| a first transmission bus...having a first programmable transmitting or receiving data rate, a first programmable...signal swing | The memory bus between the A16's IMC and the LPDDR5 DRAM. Programmability is allegedly achieved via the IMC using the DVFS features of LPDDR5 to control frequency (data rate) and voltage (signal swing). | ¶¶39-40 | col. 5:21-44 |
| a logic unit coupled to the first transmission bus for accessing the type of memory cell array group | The integrated memory controller (IMC) within the A16 Bionic chip. | ¶41 | col. 4:9-12 |
| a second transmission bus coupled between the logic unit and the ASIC processor having a second programmable...data rate, a second programmable...signal swing | An internal bus coupling the IMC to the ASIC processor cores within the A16. Programmability is allegedly achieved via mechanisms such as Collaborative Processor Performance Control (CPPC) that alter on-chip operating frequency and voltage. | ¶¶43-47 | col. 5:21-44 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the term "logic unit," which the patent specification motivates as a way to bridge components from different semiconductor process generations, can be construed to read on an "integrated memory controller" (IMC) that is fabricated on the same monolithic silicon die as the "ASIC processor".
- Technical Questions: The complaint alleges the bus between the IMC and processor cores is programmable via CPPC. A point of contention may be whether CPPC, a mechanism for managing processor core performance states (frequency and voltage), constitutes direct programming of the bus data rate and signal swing as required by the claim, or if it is an indirect system-level control. An annotated image provided in the complaint identifies the alleged "first transmission bus" and "second transmission bus" on a die shot of the A16 chip (Compl. p. 25).
10,998,017 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a DRAM core cell...supplied with a first voltage...lower than 1.1V | The core cells of the LPDDR5 DRAM, which allegedly operate using power from the VDD2H or VDD2L voltage rails, both of which are specified to be below 1.1V. | ¶¶57-58 | col. 6:1-4 |
| a peripheral circuit...supplied with a second voltage...lower than 1.1V | Buffers and data path circuits within the LPDDR5 DRAM, which are also allegedly powered by the VDD2H or VDD2L rails operating below 1.1V. | ¶59 | col. 6:5-10 |
| wherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell | The LPDDR5 DRAM within the A16 package is alleged to be formed on a single chip with peripheral circuits external to the core memory arrays. | ¶60 | col. 6:11-14 |
| wherein the first voltage and the second voltage are capable of making the DRAM be applied to an embedded display port (eDP) | The Accused Products allegedly utilize an eDP protocol for communication with displays. | ¶61 | col. 6:15-17 |
- Identified Points of Contention:
- Scope Questions: The complaint's allegation for the "eDP" limitation is that the accused devices "utilize an eDP protocol." This raises the question of whether the claim term "capable of making the DRAM be applied" requires that the accused DRAM is actually used as an eDP frame buffer, or if the mere technical capability is sufficient for infringement.
- Technical Questions: Infringement depends on mapping the LPDDR5 standard's voltage rails (VDD2H/VDD2L) to the claimed "DRAM core cell" and "peripheral circuit". A technical dispute may arise over the precise boundaries of these elements within a modern DRAM architecture. The complaint provides a JEDEC workshop diagram illustrating distinct "Core" and "Peri" (peripheral) blocks to support this distinction (Compl. p. 30).
V. Key Claim Terms for Construction
The Term: "logic unit" (from ’834 Patent, Claim 21)
- Context and Importance: The construction of this term is critical to determining whether an Integrated Memory Controller (IMC), which is part of the same monolithic silicon die as the processor cores, falls within the scope of the claim. Practitioners may focus on this term because the patent's specification repeatedly motivates the invention as a solution for integrating components from different semiconductor process generations.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language defines the term functionally: "a logic unit coupled to the first transmission bus for accessing the type of memory cell array group" (’834 Patent, col. 8:51-53). It does not explicitly require the logic unit to be on a separate chip or made with a different process technology.
- Evidence for a Narrower Interpretation: The "Description of the Prior Art" section states that "memory semiconductor process generations are typically more advanced and different from logic unit semiconductor process generations" (’834 Patent, col. 1:35-39). This context suggests the invention was conceived to solve a problem that may not exist when the logic unit and processor are integrated.
The Term: "peripheral circuit" (from ’017 Patent, Claim 1)
- Context and Importance: The definition of this term is central to the infringement analysis, which maps specific power rails from the LPDDR5 standard to the claimed "peripheral circuit" and "DRAM core cell." The viability of this mapping depends on how these architectural elements are defined.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent specification refers to a "peripheral circuit unit 104" that is electrically connected to the "memory core unit 102" (’017 Patent, col. 4:60-62; Fig. 1). A broad reading could encompass all on-chip circuitry that is not part of the core memory array itself, such as control logic and data path buffers.
- Evidence for a Narrower Interpretation: The specification links the power consumption of the peripheral circuit unit to "access power consumption" (’017 Patent, col. 5:50-51). This could support an argument that the term is limited to only those circuits directly involved in memory access operations, potentially excluding other on-chip logic powered by the same voltage source.
VI. Other Allegations
- Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, stating that Apple encourages infringement through its affirmative acts of manufacturing, selling, and providing instructions, product manuals, and technical support that direct customers to use the accused products in an infringing manner (e.g., Compl. ¶¶48-49). The complaint also alleges contributory infringement, asserting that the accused components are material to the inventions, are not staple articles of commerce, and have no substantial non-infringing uses (e.g., Compl. ¶50).
- Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. Pre-suit knowledge is alleged on the basis that Apple, as a major technology company, "regularly monitors memory module technology advances." Alternatively, it alleges willful blindness, claiming Apple has a policy of not reviewing the patents of others. Post-suit knowledge is based on the filing of the instant lawsuit (Compl. ¶¶30-31).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural scope: For the ’834 and ’942 patents, can the term "logic unit," which the specifications describe in the context of bridging components from different manufacturing processes, be construed to cover an "integrated memory controller" (IMC) fabricated on the same monolithic silicon die as the "ASIC processor"?
- A key evidentiary question will be one of functional mapping: For the DRAM power management patents (’017, ’098, ’652), does the operation of the accused LPDDR5 memory, with its standardized voltage domains (e.g., VDD2H, VDD2L, VDDQ), correspond to the distinct functions and structures of the claimed "DRAM core cell," "peripheral circuit," and "input/output circuit," or is there a fundamental mismatch in how the claim elements map to the real-world device?
- A central technical question will be one of programmability: For the ’834 and ’942 patents, does the accused products' use of system-level performance controls like DVFS and CPPC constitute the direct "programmable" control over bus data rates and signal swings required by the claims, or is this an indirect effect of managing processor core states?