Memray MT LLC v. Hewlett Packard Enterprises Co

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Memray MT LLC (Texas)
  • Defendant: Hewlett Packard Enterprise Company (Delaware)
  • Plaintiff’s Counsel: Parker, Bunt & Ainsworth, P.C.; Nixon Peabody LLP
• Case Identification: 2:25-cv-00970, E.D. Tex., 09/22/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains regular and established places of business in the district, including specific office locations in Frisco and Plano, Texas.
• Core Dispute: Plaintiff alleges that Defendant’s server products infringe two patents related to methods for improving the efficiency of data transfers between a coprocessor (e.g., a GPU) and non-volatile memory (e.g., an SSD).
• Technical Context: The technology addresses performance bottlenecks in high-performance computing systems where latency caused by redundant data copies and software overhead can limit the speed of data-intensive applications.
• Key Procedural History: The complaint notes that U.S. Patent No. 10,303,597 is a continuation of U.S. Patent No. 10,013,342, indicating a shared specification and related claim scope.

Case Timeline

Date	Event
2016-02-15	’342 and ’597 Patents - Earliest Priority Date
2018-07-03	’342 Patent - Issue Date
2019-05-28	’597 Patent - Issue Date
2025-09-22	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,013,342 - "Computing Device, Data Transfer Method Between Coprocessor and Non-volatile Memory, and Computer-Readable Recording Medium", issued July 3, 2018

The Invention Explained

• Problem Addressed: The patent describes a technical problem in conventional computing systems where a coprocessor (like a GPU) and non-volatile memory (like an SSD) are "completely disconnected from each other and are managed by different software stacks" (Compl. ¶25; ’342 Patent, col. 1:40-43). This separation creates significant performance overhead due to "redundant memory allocations/releases and data copies" between user-space and kernel-space, as well as "kernel-mode and user-mode switching overheads," which contribute to high latency in data transfers (Compl. ¶25; ’342 Patent, col. 1:43-53).
• The Patented Solution: The invention provides a computing device and method that create a more direct data path to reduce these overheads (Compl. ¶27). The solution involves a software architecture comprising a "controller driver" and a "library" executed by the main CPU (’342 Patent, col. 2:1-5). The controller driver maps the coprocessor's memory to a "system memory block" within the CPU's main memory, and the library then moves data directly between the coprocessor and the non-volatile memory "via" this shared system memory block, bypassing the conventional, inefficient software layers (Compl. ¶28; ’342 Patent, col. 2:5-8).
• Technical Importance: This approach aims to minimize CPU intervention and redundant data copies, thereby reducing latency for data-intensive applications that rely on hardware accelerators like GPUs (Compl. ¶27).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 (Compl. ¶41).
• Claim 1 essential elements:
  • A computing device comprising a CPU, CPU memory, non-volatile memory, a coprocessor, and coprocessor memory.
  • A recording medium including a "controller driver" for the non-volatile memory and a "library" that are executed by the CPU.
  • The controller driver is configured to "map the coprocessor memory to a system memory block of the CPU memory."
  • The library is configured to "move data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory."
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 10,303,597 - "Computing Device, Data Transfer Method Between Coprocessor and Non-volatile Memory, and Computer-Readable Recording Medium", issued May 28, 2019

The Invention Explained

• Problem Addressed: As a continuation of the ’342 Patent, the ’597 Patent addresses the same technical problem of inefficient data movement between disconnected coprocessors and non-volatile memory devices, which leads to performance degradation from software overheads (Compl. ¶¶ 19, 25; ’597 Patent, col. 1:45-56).
• The Patented Solution: The solution is an improved "memory management device" that streamlines data transfers (Compl. ¶23; ’597 Patent, Abstract). It uses a controller driver to "expose" a memory space within the CPU's memory system to the coprocessor. A corresponding library then moves data between the coprocessor and non-volatile memory using this exposed memory space as a direct conduit, thereby reducing the need for the multiple data-copying steps found in conventional systems (Compl. ¶¶ 28-29; ’597 Patent, col. 2:1-8).
• Technical Importance: The invention provides a software-based mechanism to create a high-performance data path, allowing applications to better leverage the speed of specialized coprocessors without being bottlenecked by traditional I/O stacks (Compl. ¶27).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 (Compl. ¶43).
• Claim 1 essential elements:
  • A memory management device for a computing device that includes a CPU, non-volatile memory, a coprocessor, and coprocessor memory.
  • The device comprises a "controller driver that exposes a memory space used by the CPU to the coprocessor memory."
  • It also comprises a "library that moves the data... between the coprocessor and the non-volatile memory via the memory space exposed to the coprocessor memory."
  • The controller driver manages a register that includes entries for "pointing addresses of the memory space."
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

• Product Identification: The complaint identifies the accused products as "HPE server products that comprise or otherwise implement non-volatile memory transfer and/or management" (Compl. ¶37).
• Functionality and Market Context: The complaint alleges, on information and belief, that these server products implement chips from Advanced Micro Devices, Inc. ("AMD"), Intel Corporation ("Intel"), and/or Nvidia Corporation ("Nvidia") (Compl. ¶38). The accused functionality relates to the management and transfer of data within these high-performance computing systems, which is central to their operation. The complaint does not detail the specific software architecture of the accused servers but relies on "publicly reported identification and documentation of the features, components, and functionality" (Compl. ¶39).

IV. Analysis of Infringement Allegations

The complaint alleges infringement of the asserted patents by reference to Appendices A and B, which are described as exemplary claim charts (Compl. ¶¶ 41, 43). These appendices were not attached to the publicly filed complaint. Therefore, the complaint does not provide sufficient detail for a specific analysis of how the accused products allegedly meet the limitations of the asserted claims. The infringement allegations are premised on the general functionality of HPE server products that manage data transfers between processors and non-volatile memory (Compl. ¶37).

No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Architectural Questions: A central issue may be whether the software architecture in the accused HPE servers, which likely involves complex interactions between an operating system, device drivers from multiple vendors (e.g., HPE, Intel, Nvidia), and virtualization layers, can be characterized as containing the distinct "controller driver" and "library" components recited in the claims.
  • Scope Questions: The dispute may turn on the scope of the functional language in the claims. A key question for the ’342 Patent will be what constitutes "mapping the coprocessor memory to a system memory block." For the ’597 Patent, a key question will be what actions constitute a controller driver "expos[ing] a memory space" to the coprocessor. The defense may argue that the accused products achieve data transfer through a different mechanism that does not meet these specific functional requirements.

V. Key Claim Terms for Construction

’342 Patent (Claim 1)

• The Term: "system memory block of the CPU memory"
• Context and Importance: This term defines the intermediary data structure that is central to the claimed invention. The construction of this term will determine what types of memory allocation and management schemes in the accused products can satisfy this limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself may be argued to have a plain and ordinary meaning of any designated block of memory within the CPU's address space.
  • Evidence for a Narrower Interpretation: The specification describes this block as a "kernel buffer" that may include specific structures like a "memory-mapped register and a pinned memory space mapped to the coprocessor memory" (’342 Patent, col. 2:9-12). These detailed embodiments may be used to argue for a more limited construction.

’597 Patent (Claim 1)

• The Term: "exposes a memory space"
• Context and Importance: This active verb defines the core function of the claimed "controller driver." The interpretation of "exposes" is critical to determining whether the accused drivers perform the claimed function. Practitioners may focus on this term because its level of abstraction could be a key point of dispute.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party could argue that "exposes" should be construed broadly to mean any action by which the driver makes a CPU memory region accessible to the coprocessor.
  • Evidence for a Narrower Interpretation: The specification describes the software stack in terms of a "non-volatile direct memory access (NDMA)" module that "manages a physical memory mapping" (’342 Patent, col. 8:59-62, incorporated by reference into the ’597 Patent). This could support an argument that "exposes" requires a specific type of direct mapping management, not just general accessibility.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement, stating that HPE provides "product manuals and other technical information" that instruct customers on how to use the accused servers in an infringing manner (Compl. ¶¶ 48, 50). It also alleges contributory infringement by providing components that are "specially made or adapted for use in infringement" and are not staple articles of commerce (Compl. ¶¶ 53-54).
• Willful Infringement: Willfulness is alleged based on HPE's purported knowledge of the patents "no later than the filing or service of this complaint" or being "willfully blind" to the infringement (Compl. ¶46). The complaint further alleges that HPE "deliberately and intentionally continued to infringe with reckless disregard for Memray's patent rights" (Compl. ¶56).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural mapping: does the complex software stack of the accused HPE servers—integrating proprietary software, an operating system kernel, and third-party drivers—contain the distinct "controller driver" and "library" components as recited in the claims, or does it implement data transfer using a different architecture that falls outside the claim scope?
• A second key issue will be one of definitional scope: can the functional claim limitations, such as "mapping the coprocessor memory to a system memory block" and "exposes a memory space," be construed to read on the specific memory management and data transfer protocols used in modern server environments, or do the detailed embodiments in the patent specification require a narrower interpretation that the accused products do not meet?