DCT

2:25-cv-00975

Induction Devices LLC v. Racetrac Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-975, E.D. Tex., 09/23/2025
  • Venue Allegations: Venue is based on Defendant having a regular and established place of business in Frisco, Texas, within the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s provision and promotion of EMVCo-compliant credit card readers induces infringement of five patents related to semiconductor circuit design, secure memory systems, and digital signal processing.
  • Technical Context: The patents-in-suit relate to fundamental semiconductor technologies for managing circuit resets, reducing signal jitter, securing data, and processing signals, which are foundational to the operation of modern complex electronics like payment terminals.
  • Key Procedural History: The complaint notes that U.S. Patent No. 7,899,145 was previously litigated in the Western District of Texas in two cases filed in 2021, which were resolved before any substantive matters were addressed.

Case Timeline

Date Event
2005-09-02 U.S. Patent No. 7,899,145 Priority Date
2006-01-26 U.S. Patent No. 7,449,926 Priority Date
2006-12-21 U.S. Patent No. 8,190,885 Priority Date
2007-03-09 U.S. Patent No. 8,370,543 Priority Date
2007-04-17 U.S. Patent No. 8,543,628 Priority Date
2008-11-11 U.S. Patent No. 7,449,926 Issued
2011-03-01 U.S. Patent No. 7,899,145 Issued
2012-05-29 U.S. Patent No. 8,190,885 Issued
2013-02-05 U.S. Patent No. 8,370,543 Issued
2013-09-24 U.S. Patent No. 8,543,628 Issued
2021 Prior litigation involving the ’145 patent was initiated in the W.D. of Texas.
2025-09-23 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - “Circuit for Asynchronously Resetting Synchronous Circuit,” Issued Nov. 11, 2008

The Invention Explained

  • Problem Addressed: The patent’s background describes the problem that a synchronous circuit, such as a RAM, may lose its stored data if it is reset with an asynchronous signal during operation; however, if an internal circuit like a CPU is operating abnormally, it may require an immediate asynchronous reset to prevent failure of the entire semiconductor device (’926 Patent, col. 2:32-54).
  • The Patented Solution: The invention is a reset signal generation circuit that intelligently chooses the type of reset signal to generate based on the circuit’s operational state (’926 Patent, Abstract). An operation detection circuit determines if a synchronous circuit (like a CPU) is "operating normally or abnormally"; based on this determination, a signal control circuit generates either a data-preserving synchronous reset signal during normal operation or an immediate, initializing asynchronous reset signal during abnormal operation (’926 Patent, col. 6:58-7:6).
  • Technical Importance: This selective reset functionality enhances the operational reliability of semiconductor devices by applying the appropriate reset strategy for different system states (Compl. ¶11).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶32).
  • Claim 1 requires:
    • A reset signal generation circuit for generating a first reset signal for a synchronous circuit.
    • An operation detection circuit to detect if the synchronous circuit is operating normally or abnormally.
    • A signal control circuit that generates the first reset signal based on a system reset signal, a clock signal, and the operation detection signal.
    • The signal control circuit generates a synchronous first reset signal when the circuit operates normally.
    • The signal control circuit generates an asynchronous first reset signal when the circuit operates abnormally.
  • The complaint reserves the right to assert additional claims (Compl. ¶33).

U.S. Patent No. 7,899,145 - “Circuit, System, and Method for Multiplexing Signals with Reduced Jitter,” Issued Mar. 1, 2011

The Invention Explained

  • Problem Addressed: In high-speed electronic systems, multiplexers that select between different clock signals can introduce timing uncertainties known as jitter. The patent explains that conventional multiplexer designs add "crosstalk and power supply noise to the clock path," which degrades system performance and reliability (’145 Patent, col. 2:60-63; Compl. ¶16).
  • The Patented Solution: The patent discloses a multiplexer circuit designed to reduce jitter by physically and electrically isolating signal paths (’145 Patent, Abstract). The circuit arranges its logic gates in "separate power domains" and uses a logic block to deactivate one of the input signal paths. By ensuring only one signal is active, the circuit prevents noise and crosstalk from the inactive path from interfering with the selected signal path (’145 Patent, col. 3:13-28; Compl. ¶17).
  • Technical Importance: By minimizing jitter in clock networks, this technology enables more reliable operation of high-speed synchronous systems (Compl. ¶16).

Key Claims at a Glance

  • The complaint asserts independent claim 10 (Compl. ¶42).
  • Claim 10 requires a system comprising:
    • A circuit with two logic gates, a first logic block, and a second logic block, with each component "arranged within a separate power supply domain."
    • A first logic gate coupled to a first signal.
    • A second logic gate coupled to a second signal.
    • A second logic block coupled to one of the first and second signals, based on a control signal.
    • A system component coupled to the second logic block.
  • The complaint reserves the right to assert additional claims (Compl. ¶43).

U.S. Patent No. 8,190,885 - “Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions,” Issued May 29, 2012

  • Technology Synopsis: The patent addresses security vulnerabilities in near field communication (NFC) systems. The invention describes a memory module that tightly integrates a security processor, non-volatile memory, and an NFC radio frequency component to create a secure environment for processing and storing transaction data, thereby preventing unauthorized access and ensuring data integrity (’885 Patent, Abstract; Compl. ¶21-22).
  • Asserted Claims: The complaint asserts at least claims 1 and 3 (Compl. ¶52).
  • Accused Features: The complaint alleges that the EMVCo-compliant credit card readers enable secure contactless transactions that practice the claimed invention (Compl. ¶52).

U.S. Patent No. 8,370,543 - “Busy Detection Logic for Asynchronous Communication Port,” Issued Feb. 5, 2013

  • Technology Synopsis: This patent addresses the technical challenge of synchronizing communication between components operating in different clock domains (e.g., a fast processor and a slower memory device). The invention provides systems and methods for synchronizing device resource access information without imposing restrictive requirements on signal pulse widths or needing high-speed clocks, which reduces circuit complexity and power consumption (’543 Patent, Abstract; Compl. ¶25-27).
  • Asserted Claims: The complaint asserts at least claim 16 (Compl. ¶62, ¶69).
  • Accused Features: The complaint alleges that the internal operations of the EMVCo-compliant credit card readers require synchronization between different time domains in a manner that practices the claimed invention (Compl. ¶62).

U.S. Patent No. 8,543,628 - “Method and System of Digital Signal Processing,” Issued Sep. 24, 2013

  • Technology Synopsis: The patent is directed to a dynamically reconfigurable digital filtering system on a chip. An instruction set from a microcontroller configures a controller and an address-calculation device to select filter coefficients, and a data path device then uses these coefficients to perform digital signal processing on incoming data, enabling efficient and scalable resource use (’628 Patent, Abstract; Compl. ¶29-30).
  • Asserted Claims: The complaint asserts at least claim 1 (Compl. ¶72).
  • Accused Features: The complaint alleges that the signal processing functions within the EMVCo-compliant credit card readers practice the claimed invention (Compl. ¶72).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the accused products as "EMVCo-compliant credit card readers" (the "Accused Instrumentalities") (Compl. ¶32).

Functionality and Market Context

  • The complaint alleges that Defendant provides, promotes, and supports these readers, which "enable and encourage customers to use contactless consumer credit cards in payment transactions" (Compl. ¶32, ¶42). The complaint does not provide specific technical details about the internal architecture or operation of any particular make or model of credit card reader. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references, but does not attach, claim chart exhibits purporting to show infringement for each asserted patent (Compl. ¶33, ¶43, ¶53, ¶63, ¶73). In the absence of these exhibits, the infringement theory must be summarized from the complaint’s narrative allegations.

For both the ’926 and ’145 patents, the complaint alleges that the Accused Instrumentalities, when used by customers for contactless payments, directly infringe the asserted claims (Compl. ¶32, ¶42). The narrative suggests that for these readers to function reliably and meet industry standards like EMVCo, they must necessarily incorporate the patented technologies. For the ’926 patent, this implies the need for sophisticated reset circuitry to handle potential errors during a transaction. For the ’145 patent, this implies the need for low-jitter signal multiplexing to process high-speed payment data accurately. The complaint, however, does not contain specific factual allegations detailing the actual internal components of the accused readers or mapping them to the elements of the asserted claims.

  • Identified Points of Contention:
    • Evidentiary Questions: A primary issue may be whether the complaint provides sufficient factual matter to state a plausible claim for relief. The infringement allegations are based on the purported functional requirements of an "EMVCo-compliant" device rather than on a direct analysis of the accused products' specific architecture. The question for the court will be what evidence the complaint provides that the accused readers actually contain the specific circuit configurations required by the claims.
    • Scope Questions: The case may raise questions about whether compliance with an industry standard like EMVCo necessitates the use of the specific structures claimed in the patents. For instance, with respect to the ’145 patent, a question is whether the term "separate power supply domain" requires specific physical and electrical isolation structures that are present in the accused devices, or if it can be read more broadly on less distinct forms of power management.

V. Key Claim Terms for Construction

  • Term ('926 Patent, Claim 1): "operating normally or abnormally"
    • Context and Importance: The distinction between "normal" and "abnormal" operation is the trigger for the claimed invention's selective generation of either a synchronous or asynchronous reset signal. The construction of this term will be critical to determining whether the monitoring and reset functions within the accused readers meet this core limitation.
    • Intrinsic Evidence for a Broader Interpretation: The specification describes an abnormal operation as a state where "a clear signal is not provided from the CPU 11 to the operation detection circuit 21 at the appropriate interval" (’926 Patent, col. 4:38-41). This could be interpreted to cover any failure of a component to perform a periodic "check-in" or respond to a watchdog timer.
    • Intrinsic Evidence for a Narrower Interpretation: The description of the preferred embodiment focuses on a specific implementation where an "up-counter" exceeds a "predetermined value" because the CPU fails to provide a clear signal (’926 Patent, col. 4:21-34). This could support a narrower construction limited to specific counter-based watchdog mechanisms.
  • Term ('145 Patent, Claim 10): "each arranged within a separate power supply domain"
    • Context and Importance: This limitation is central to the ’145 patent’s claimed solution for reducing jitter by isolating noise sources. The infringement analysis will depend on the degree of physical and electrical separation required to constitute a "separate" domain. Practitioners may focus on this term because it defines the core structural basis for the alleged technical improvement over the prior art.
    • Intrinsic Evidence for a Broader Interpretation: The specification states that a component arranged in a separate power domain is "supplied with its own power bus and physically separated from components arranged in other power domains" (’145 Patent, col. 6:50-53). This language may support an interpretation that covers any distinct power bus routing.
    • Intrinsic Evidence for a Narrower Interpretation: The patent also describes using "supply guard rings for further isolation" and locating components in different "supply islands" (’145 Patent, col. 6:58-60). This could support a narrower definition requiring more robust and specific isolation techniques beyond simple bus separation.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement to infringe under 35 U.S.C. § 271(b). The alleged inducing acts include the "provision, promotion, and support of EMVCo-compliant credit card readers" and providing "instruction materials, training, and services regarding the Accused Instrumentalities" (Compl. ¶32, ¶37). The complaint alleges that Defendant possessed the requisite specific intent to induce infringement "since at least the time Defendant received notice" via the complaint itself (Compl. ¶36-37).
  • Willful Infringement: Willfulness is alleged based on Defendant’s continued inducement after being made aware of the patents and its alleged infringement by the filing of the complaint (Compl. ¶38, ¶48).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of evidentiary pleading standards: Does the complaint's reliance on the functional requirements of an industry standard (EMVCo) provide sufficient plausible factual allegations to support a claim of infringement of these highly technical, semiconductor-level patents, absent specific details about the accused readers' internal architecture?
  • A key technical question will be one of functional necessity versus claimed structure: Does achieving reliable operation in a modern payment terminal necessarily require the specific circuit architectures recited in the asserted claims (e.g., a selective synchronous/asynchronous reset circuit, a multiplexer with separated power domains), or can the same functional performance be achieved through alternative, non-infringing designs?
  • The case will also present a question of intent for inducement: Can Plaintiff establish that Defendant, by providing industry-standard payment readers, possessed the specific intent to encourage infringement of these particular patents, especially where the complaint alleges knowledge only as of the date of its own filing?