DCT

2:25-cv-01006

Induction Devices LLC v. Capital One Financial Corp

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: Induction Devices LLC (Texas)
- Defendant: Capital One Financial Corporation (Delaware) and Capital One, N.A. (United States)
- Plaintiff’s Counsel: Shea | Beaty PLLC
Case Identification: 2:25-cv-01006, E.D. Tex., 10/03/2025
Venue Allegations: Plaintiff alleges venue is proper because each Defendant has a regular and established place of business in the Eastern District of Texas and has committed acts of infringement there.
Core Dispute: Plaintiff alleges that Defendant’s contactless credit cards infringe seven patents related to fundamental semiconductor technologies, including circuit resets, signal multiplexing, secure memory, and digital signal processing.
Technical Context: The patents-in-suit address low-level circuit design and system architecture challenges that are foundational to the operation of complex semiconductor chips used in modern electronics, including financial smart cards.
Key Procedural History: The '145 patent was previously litigated, but the cases were resolved before substantive matters were addressed. For all asserted patents, Plaintiff alleges that Defendants were made aware of them on September 9, 2025, due to their involvement in a related case, [Induction Devices LLC](https://ai-lab.exparte.com/party/induction-devices-llc) v. BPS Direct LLC. The complaint also notes that two patents, U.S. Patent Nos. 6,868,500 and 6,931,465, have expired, and seeks damages only for a statutorily limited pre-expiration period.

Case Timeline

Date	Event
2000-10-26	Priority Date for U.S. Patent No. 6,868,500
2001-03-31	Priority Date for U.S. Patent No. 6,931,465
2005-03-15	U.S. Patent No. 6,868,500 Issued
2005-08-16	U.S. Patent No. 6,931,465 Issued
2008-11-11	U.S. Patent No. 7,449,926 Issued
2011-03-01	U.S. Patent No. 7,889,145 Issued
2012-05-29	U.S. Patent No. 8,190,885 Issued
2013-02-05	U.S. Patent No. 8,370,543 Issued
2013-09-24	U.S. Patent No. 8,543,628 Issued
2019-10-03	Damages Period Begins for Expired Patents
2022-06-09	U.S. Patent No. 6,931,465 Expires
2023-01-23	U.S. Patent No. 6,868,500 Expires
2025-09-09	Date of Alleged Notice to Defendants of Patents-in-Suit
2025-10-03	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - "Circuit for Asynchronously Resetting Synchronous Circuit," issued November 11, 2008

The Invention Explained

Problem Addressed: Synchronous circuits, such as CPUs and memory, require reset signals to initialize properly. The technical challenge is to perform this reset in a way that preserves data during normal operation but acts immediately during an abnormal event, such as a power fluctuation or system error (Compl. ¶¶ 12-13).
The Patented Solution: The invention is a reset signal generation circuit that intelligently chooses the type of reset signal to generate. It produces a synchronous reset signal (timed with the system clock) when the CPU is operating normally, which can preserve data in RAM. It generates an asynchronous reset signal (immediate, not timed to the clock) when the CPU is operating abnormally, forcing an immediate initialization of all synchronous circuits (Compl. ¶¶ 12-13; ’926 Patent, Ex. A at 6:58-7:6). The circuit's decision can also be based on the power supply voltage level (Compl. ¶14; ’926 Patent, Ex. A at 7:7-15).
Technical Importance: This selective approach enhances the reliability of a semiconductor device by allowing for both safe, data-preserving resets and rapid, system-saving resets depending on the operational context (Compl. ¶13).

Key Claims at a Glance

The complaint asserts independent claim 1 (Compl. ¶45).
The complaint does not provide the language of the asserted claim.
Plaintiff reserves the right to amend its infringement analysis, which may involve the assertion of additional claims (Compl. ¶46).

U.S. Patent No. 7,889,145 - "Circuit, System, and Method for Multiplexing Signals with Reduced Jitter," issued March 1, 2011

The Invention Explained

Problem Addressed: In high-speed synchronous systems, managing the timing of clock signals is critical. Prior art multiplexer circuits, used to select between different clock signal sources (like phase-locked loops), often introduced undesirable side effects such as crosstalk and power supply noise, which degrade system performance and reliability (Compl. ¶18; ’145 Patent, Ex. B at 1:49-52, 2:60-63).
The Patented Solution: The patent describes an improved multiplexer circuit architecture. The core innovation is a logic block that deactivates one of the input signals by supplying a static control signal, ensuring that only one signal is active at the inputs of the logic gates at any given time (Compl. ¶19; ’145 Patent, Ex. B at 3:13-26). This prevents the signals from interfering with each other (crosstalk) and reduces noise. The patent also teaches placing the logic gates in separate power domains for further isolation (Compl. ¶19; ’145 Patent, Ex. B at 3:26-28).
Technical Importance: This design eliminates a key source of jitter and noise in clock paths, leading to more stable and reliable high-frequency circuit operation (Compl. ¶17).

Key Claims at a Glance

The complaint asserts independent claim 10 (Compl. ¶55).
The complaint does not provide the language of the asserted claim.
Plaintiff reserves the right to amend its preliminary infringement analysis (Compl. ¶56).

U.S. Patent No. 8,190,885 - "Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions," issued May 29, 2012

Technology Synopsis: The patent is directed to a memory module that integrates non-volatile memory, a security processor, and a near field communication (NFC) radio component into a single, secure system (Compl. ¶23). This tight integration allows for secure storage and processing of NFC transaction data, the creation of memory partitions with individualized access rights, and secure logging of transactions (Compl. ¶24).
Asserted Claims: The complaint asserts independent claims 1 and 3 (Compl. ¶65).
Accused Features: The complaint alleges that Defendants' contactless credit cards incorporate this integrated secure memory and NFC architecture (Compl. ¶65).

U.S. Patent No. 8,370,543 - "Busy Detection Logic for Asynchronous Communication Port," issued February 5, 2013

Technology Synopsis: The patent describes a method for synchronizing access to a shared resource (like memory) between two components operating in different, independent time domains (e.g., a fast processor and a slower memory device) (Compl. ¶27). The invention purports to solve this problem without requiring high-speed clocks or imposing restrictions on the pulse width of control signals, which were limitations of prior art solutions that increased complexity and power consumption (Compl. ¶¶ 28-29).
Asserted Claims: The complaint asserts at least claim 16 (Compl. ¶75). The infringement analysis referenced in the complaint refers to claim 1, suggesting it may be the asserted independent claim (Compl. ¶76).
Accused Features: The complaint alleges that the complex chips within contactless credit cards require such synchronization logic to manage communication between different internal components operating at different clock speeds (Compl. ¶75).

U.S. Patent No. 8,543,628 - "Method and System of Digital Signal Processing," issued September 24, 2013

Technology Synopsis: The patent is directed to a programmable and dynamically reconfigurable system-on-a-chip for digital signal processing (DSP) (Compl. ¶31). The system uses instruction sets from a microcontroller to configure a controller and an address-calculation device, which in turn select filter-coefficients to perform DSP operations (like digital filtering) on incoming data, offering benefits such as resource efficiency and scalability (Compl. ¶¶ 31-32).
Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶85).
Accused Features: The complaint alleges that contactless credit cards utilize this type of programmable DSP architecture for processing communication signals (Compl. ¶85).

U.S. Patent No. 6,868,500 - "Power on Reset Circuit for a Microcontroller," issued March 15, 2005

Technology Synopsis: The patent addresses the problem that conventional Power on Reset (POR) circuits in microcontrollers only handle initial boot-up and fail to address power stability issues that arise post-boot, or do so by dedicating scarce system resources (’500 Patent, col. 1:58-62). The invention discloses a robust POR circuit that not only provides multi-level POR capabilities but also utilizes the same resources to perform post-boot-up power stability functions, such as controlling the microcontroller’s switch mode pump (SMP) (’500 Patent, col. 2:44-59).
Asserted Claims: The complaint asserts independent claim 22 (Compl. ¶95).
Accused Features: The complaint alleges that Defendants' use of the contactless credit cards performs the method steps claimed by the patent related to power management and reset functions (Compl. ¶¶ 95, 97).

U.S. Patent No. 6,931,465 - "Intelligent, Extensible SIE Peripheral Device," issued August 16, 2005

Technology Synopsis: The patent explains that conventional serial interface engines (SIEs) for peripheral devices act merely as a conduit, passing all communication requests to an external processor, which reduces performance (’465 Patent, col. 1:38-40). The invention provides an "intelligent" SIE that can autonomously process basic protocol requests itself and only delegates unrecognized or more complex requests to the external processor, thereby increasing performance and reducing overhead (’465 Patent, col. 1:45-52, 3:52-55).
Asserted Claims: The complaint asserts independent claim 13 (Compl. ¶100).
Accused Features: The complaint alleges that Defendants' use of the contactless credit cards, which must communicate with payment terminals, performs the patented method of intelligently handling communication requests (Compl. ¶¶ 100, 102).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are "contactless credit cards" made, used, sold, or provided by Defendants (Compl. ¶45).

Functionality and Market Context

The complaint alleges these are standard financial products issued to customers for making payments (Compl. ¶¶ 97, 102). The complaint does not describe the specific technical operation or internal components of the accused cards in detail. The infringement allegations are premised on the inference that, in order to function as modern contactless payment devices, these cards must necessarily contain complex semiconductor chips that incorporate the technologies covered by the patents-in-suit, such as advanced power management, high-speed clocking circuits, and secure NFC communication modules (Compl. ¶¶ 45, 55, 65).

IV. Analysis of Infringement Allegations

The complaint references claim-chart exhibits for each asserted patent but does not attach or include them in the provided document. Therefore, the infringement theories are summarized below in prose.

'926 Patent Infringement Allegations

The complaint alleges that the semiconductor chips within the accused contactless credit cards contain synchronous circuits like CPUs and memory that require reliable reset functionality (Compl. ¶¶ 12-13, 45). The infringement theory suggests that to operate reliably during a financial transaction while also being able to handle unexpected events like power loss or communication errors, these chips must implement a reset circuit that selectively generates either a data-preserving synchronous reset (for normal operations) or an immediate asynchronous reset (for abnormal operations), thereby practicing the method of asserted claim 1 (Compl. ¶46).

'145 Patent Infringement Allegations

The complaint alleges that the high-frequency processors within the accused contactless credit cards require precise clock signals with minimal jitter and noise (Compl. ¶¶ 17-18, 55). The infringement theory posits that these cards employ multiplexing circuits to manage and select between clock signals. It is alleged that to achieve the required level of performance, these multiplexers are designed to eliminate crosstalk and noise by ensuring only one signal path is active at a time, a technique allegedly covered by asserted claim 10 (Compl. ¶56).

Identified Points of Contention

Evidentiary Questions: The complaint's allegations regarding the specific, internal circuit-level architecture of the chips inside the accused credit cards are made on "information and belief." A central point of contention may be what, if any, pre-suit investigation or reverse engineering Plaintiff performed to support the inference that these highly specific patented designs are actually implemented, as opposed to alternative, non-infringing designs that achieve similar high-level functionality.
Technical Questions: For the '926 patent, a key question may be whether the error-handling or power-management functions in the accused cards constitute the specific detection of an "abnormal" operation state that triggers an asynchronous reset, as required by the claim, or if they rely on more generic reset mechanisms. For the '145 patent, a question may be whether the accused clock multiplexers actually use the claimed method of deactivating one signal path with a "static control signal" to reduce jitter, or if they employ other common jitter-reduction techniques.

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

The complaint does not provide the language of the asserted independent claims for the lead patents. Analysis is based on the complaint's characterization of the technology.

For the '926 Patent

The Term: "operating normally or abnormally"
Context and Importance: This phrase appears to be the core condition that dictates whether the claimed circuit generates a synchronous or an asynchronous reset signal (Compl. ¶12). The scope of infringement will depend heavily on what technical conditions within the accused device are defined as "normal" versus "abnormal."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification may describe "abnormal" operation in general terms, such as any deviation from expected program execution or any drop in power supply voltage, potentially capturing a wide range of error and power states in the accused devices (Compl. ¶14).
- Evidence for a Narrower Interpretation: The patent may define "abnormal" operation more narrowly, linking it to the state of a specific operation detection circuit or a CPU-generated clear signal (Compl. ¶13). Such a definition might require Plaintiff to show a more specific mechanism is present in the accused cards.

For the '145 Patent

The Term: "deactivating one of the first and second signals"
Context and Importance: This term describes the key step in the patented solution for eliminating crosstalk and noise in a multiplexer (Compl. ¶19). The infringement analysis may turn on the precise technical meaning of "deactivating."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification could describe "deactivating" in a functional way, covering any method that prevents a signal from propagating to the output, such as simple logic gating.
- Evidence for a Narrower Interpretation: The patent's focus on supplying a "static control signal to the first and second logic gates" to ensure only one is active could support a narrower construction requiring a specific circuit implementation, potentially excluding other methods of signal isolation (Compl. ¶19).

VI. Other Allegations

Indirect Infringement

For each asserted patent, the complaint alleges induced infringement. It claims Defendants, with specific intent or willful blindness, encourage infringement by partners, clients, and end users through actions like advertising, distributing the accused cards, and providing instruction materials (e.g., Compl. ¶¶ 49-50, 59-60). The basis for knowledge is Defendants' alleged awareness of the patents as of September 9, 2025, from their involvement in a related lawsuit (e.g., Compl. ¶48, 58).

Willful Infringement

Willfulness is alleged for all patents based on Defendants' continued infringement after having received notice of the patents on September 9, 2025 (e.g., Compl. ¶¶ 51, 61).

VII. Analyst’s Conclusion: Key Questions for the Case

A central issue will be evidentiary: Given that the infringement allegations concern highly specific, internal circuit designs within semiconductor chips, what factual basis will emerge during discovery to support the complaint's "information and belief" pleading that the accused contactless cards practice these particular patented inventions, as opposed to utilizing alternative, commercially available, or public-domain solutions for functions like circuit reset and clock signal management?
The case may turn on a question of technical mapping: Can Plaintiff successfully demonstrate that the high-level functions of a consumer financial product (e.g., error handling during a transaction) map directly onto the specific circuit-level operations required by the claims? For instance, does an error in an NFC transaction qualify as the "abnormal operation" that triggers the selective asynchronous reset claimed in the '926 patent?
A key legal question will concern knowledge and intent: The allegations of inducement and willfulness are tied directly to a specific date of notice derived from a related litigation. The case will likely test the sufficiency of this notice to establish the specific intent required for inducement and the "egregious" conduct often associated with enhanced damages for willfulness.