DCT
2:25-cv-01008
Wecrevention Inc v. Lenovo Group Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: WeCrevention Inc. (Texas)
- Defendant: Lenovo Group Limited, and nine affiliated entities (China, Mexico, Hong Kong)
- Plaintiff’s Counsel: Fabricant LLP
- Case Identification: 2:25-cv-01008, E.D. Tex., 10/03/2025
- Venue Allegations: Plaintiff alleges venue is proper because Defendants are not residents of the United States and may be sued in any judicial district. The complaint further alleges that Defendants conduct substantial business in the district, including through authorized sellers and service providers.
- Core Dispute: Plaintiff alleges that Defendant’s computer products, particularly those incorporating LPDDR5 DRAM memory, infringe five U.S. patents related to reconfigurable memory module architectures and low-voltage dynamic random access memory (DRAM) operation.
- Technical Context: The technology at issue concerns methods for improving the power efficiency and data transfer flexibility of memory systems, which are critical components in battery-powered electronic devices such as laptops and tablets.
- Key Procedural History: The complaint does not reference any prior litigation, inter partes review proceedings, or licensing history concerning the patents-in-suit. Several of the asserted patents claim priority to the same set of earlier applications, indicating they are part of a related patent family.
Case Timeline
| Date | Event |
|---|---|
| 2011-10-11 | Earliest Priority Date for ’834 and ’942 Patents |
| 2012-07-17 | Earliest Priority Date for ’017, ’098, and ’652 Patents |
| 2015-10-20 | ’942 Patent Issued |
| 2015-12-01 | ’834 Patent Issued |
| 2019-09-01 | Alleged Start of Infringement (Products with LPDDR5 DRAM) |
| 2021-05-04 | ’017 Patent Issued |
| 2024-02-06 | ’098 Patent Issued |
| 2024-11-26 | ’652 Patent Issued |
| 2025-10-03 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,201,834 - “Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module,” issued December 1, 2015 (’834 Patent)
The Invention Explained
- Problem Addressed: The patent’s background section describes the limitations of standard memory modules, which are typically designed to rigid industry standards (e.g., JEDEC). This lack of flexibility can result in suboptimal power consumption and data transmission efficiency when pairing a memory module with different logic units or processors. (’834 Patent, col. 1:26-44).
- The Patented Solution: The invention proposes a memory system with two distinct data buses: a first bus between multiple memory ICs and a central logic unit, and a second bus between that logic unit and a main system processor (ASIC). The key innovation is that parameters of these buses—such as data rate, signal swing (voltage levels), and bus width—are programmable, allowing them to be reconfigured via firmware or software to optimize performance for a specific application. (’834 Patent, Abstract; col. 2:4-20).
- Technical Importance: This reconfigurability allows a single memory module hardware design to be adapted to various processors and system requirements, potentially improving power efficiency and performance without requiring a hardware redesign. (’834 Patent, col. 2:52-col. 3:15).
Key Claims at a Glance
- The complaint asserts independent claim 21. (Compl. ¶47).
- Essential elements of Claim 21 include:
- An electronics device comprising an ASIC processor and a reconfigurable memory chip module.
- The module includes a memory cell array group (with multiple memory ICs) and a logic unit.
- A first transmission bus couples the memory group to the logic unit, having a first programmable data rate and signal swing corresponding to firmware/software in the ASIC.
- A second transmission bus couples the logic unit to the ASIC, having a second programmable data rate and signal swing associated with the firmware/software.
- The complaint does not explicitly reserve the right to assert other claims.
U.S. Patent No. 10,998,017 - “Dynamic random access memory applied to an embedded display port,” issued May 4, 2021 (’017 Patent)
The Invention Explained
- Problem Addressed: The patent describes the challenge of reducing power consumption in portable devices that use panel self-refresh (PSR) for their displays. This feature requires a frame buffer, typically a DRAM, which can consume significant power if it operates at standard JEDEC-specified voltages. (’017 Patent, col. 1:47-61).
- The Patented Solution: The invention discloses a DRAM architecture where the core memory cells and the peripheral circuits operate at lower-than-standard voltages, specifically below 1.1V. This is achieved by supplying the DRAM core cell and the peripheral circuit with distinct first and second voltages, both within a low-voltage range, reducing overall power draw. (’017 Patent, Abstract; col. 2:7-16). Figure 1 illustrates the conceptual separation of the memory core unit, peripheral circuit unit, and input/output unit. (’017 Patent, FIG. 1).
- Technical Importance: Operating DRAM components at lower voltages is a fundamental method for extending battery life in mobile electronics, making this approach directly relevant to modern laptops and tablets. (’017 Patent, col. 5:1-11).
Key Claims at a Glance
- The complaint asserts independent claim 1. (Compl. ¶66).
- Essential elements of Claim 1 include:
- A DRAM comprising a DRAM core cell and a peripheral circuit.
- The DRAM core cell is supplied with a first voltage lower than 1.1V.
- The peripheral circuit is supplied with a second voltage lower than 1.1V.
- The core cell and peripheral circuit are formed on a single chip, with the peripheral circuit being "external to the DRAM core cell."
- The first and second voltages are capable of making the DRAM be applied to an embedded display port (eDP).
- The complaint does not explicitly reserve the right to assert other claims.
Multi-Patent Capsule: U.S. Patent No. 11,894,098 (’098 Patent)
- Patent Identification: U.S. Patent No. 11,894,098, "Dynamic random access memory applied to an embedded display port," issued February 6, 2024.
- Technology Synopsis: Similar to the ’017 Patent, this invention is directed to a low-power DRAM. It claims a DRAM where a core cell and an electrically connected peripheral circuit are formed on a single chip, with the core cell operating on a first voltage and the peripheral circuit on a second voltage, both below 1.1V, and where the first and second voltages are different from each other.
- Asserted Claims: The complaint asserts at least Claim 1. (Compl. ¶80).
- Accused Features: The accused features are the LPDDR5 DRAM modules in Lenovo products that support Dynamic Voltage and Frequency Scaling (DVFSC mode), which allegedly allows for different voltage rails (e.g., VDD2H and VDD2L) for the core and peripheral circuits, both below 1.1V. (Compl. ¶¶82-85).
Multi-Patent Capsule: U.S. Patent No. 12,154,652 (’652 Patent)
- Patent Identification: U.S. Patent No. 12,154,652, "Dynamic random access memory applied to an embedded display port," issued November 26, 2024.
- Technology Synopsis: This patent also relates to low-power DRAM architecture. It claims a DRAM with a core cell operating on a first voltage and an input/output (I/O) circuit operating on a third voltage, where both voltages are below 1.1V and are different from each other. The I/O circuit is described as being external to the core cell, though both are on a single chip.
- Asserted Claims: The complaint asserts at least Claim 1. (Compl. ¶93).
- Accused Features: The accused functionality is the use of separate power supply rails in the LPDDR5 DRAM module for the core cells (e.g., VDD2H/VDD2L) and the I/O circuit (e.g., VDDQ), which allegedly operate at different voltages below 1.1V. (Compl. ¶¶95, 98-100).
Multi-Patent Capsule: U.S. Patent No. 9,164,942 (’942 Patent)
- Patent Identification: U.S. Patent No. 9,164,942, "High speed memory chip module and electronics system device with a high speed memory chip module," issued October 20, 2015.
- Technology Synopsis: This invention relates to the architecture of a high-speed memory module. It describes a system where a logic unit accesses multiple memory ICs over a wide first transmission bus and then converts the data to a second, different-width set of parallel data for transmission to a main processor (ASIC) over a second bus. This architecture is designed to manage data flow efficiently between memory arrays and a processor.
- Asserted Claims: The complaint asserts at least Claim 19. (Compl. ¶108).
- Accused Features: The complaint alleges that the memory controller (MC) in the AMD Ryzen processor acts as the claimed "logic unit." It allegedly accesses the LPDDR5 DRAM module via a wide memory bus (e.g., x128) and communicates with the processor cores via an internal bus of a different width, thus infringing the claim. (Compl. ¶¶112, 114-116).
III. The Accused Instrumentality
Product Identification
- The complaint identifies "all versions and variants of Lenovo products that include LPDDR5 DRAM since September of 2019." (Compl. ¶41). Specific product lines named include IdeaPad, ThinkPad, Slim, and Yogo. The complaint uses the IdeaPad 5 Pro (16”) laptop, which incorporates an AMD Ryzen 5 6600HS Processor and 16GB of LPDDR5 DRAM, as a representative example for its allegations. (Compl. ¶¶41, 48).
Functionality and Market Context
- The infringement allegations focus on the technical operation of the LPDDR5 memory subsystem as controlled by the AMD Ryzen processor. Key accused functionalities include Dynamic Voltage and Frequency Scaling (DVFS), which allows the system to adjust memory operating frequency and voltages to save power, and the architecture of the processor’s integrated memory controller ("MC"), which manages data flow between the processor and the DRAM. (Compl. ¶¶51-54, 68). The complaint provides a technical diagram of the AMD Ryzen 6000 series processor, showing the memory controllers, CPU cores, and other components integrated on a single System-on-Chip (SoC). (Compl. p. 23).
IV. Analysis of Infringement Allegations
’834 Patent Infringement Allegations
| Claim Element (from Independent Claim 21) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an application-specific integrated circuit (ASIC) processor | The AMD Ryzen processor in the accused products, which includes multiple computing and graphics cores. | ¶49 | col. 4:6-12 |
| a type of memory cell array group, wherein the type of memory cell array group comprises multiple memory cell array ICs | The 16GB LPDDR5 DRAM module, which is comprised of multiple memory cell array ICs. | ¶50 | col. 3:38-44 |
| a first transmission bus coupled to the type of memory cell array group having a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing corresponding to firmware or software comprised in the ASIC processor | The memory bus coupling the Ryzen processor's memory controller to the LPDDR5 DRAM module. Its data rate and signal swing are allegedly programmable via firmware/software, as evidenced by LPDDR5's support for DVFS. | ¶¶51-53 | col. 4:21-31 |
| a logic unit coupled to the first transmission bus for accessing the type of memory cell array group | The memory controller ("MC") integrated within the Ryzen processor. | ¶54 | col. 4:1-5 |
| a second transmission bus coupled between the logic unit and the ASIC processor having a second programmable transmitting or receiving data rate, a second programmable transmitting or receiving signal swing associated to the firmware or the software | Internal buses within the Ryzen SoC, such as the "Infinity Fabric," which connect the memory controller to the processor cores and allegedly support dynamic frequency and voltage scaling controlled by firmware. | ¶¶55-58 | col. 4:32-41 |
- Identified Points of Contention:
- Scope Questions: A primary question may be whether the term "programmable" as used in the claim reads on the standardized, automatic power-saving functions like DVFS in LPDDR5 memory, or if it requires a higher level of reconfigurability not present in the accused products.
- Technical Questions: The complaint identifies the memory controller within the Ryzen processor as the "logic unit" and the Ryzen processor itself as the "ASIC processor." A potential point of dispute is whether these integrated components of a single SoC can be properly characterized as two separate elements as required by the claim.
’017 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a DRAM core cell, wherein the DRAM core cell is supplied with a first voltage... wherein the first voltage is lower than 1.1V | The core circuitry of the LPDDR5 DRAM module, which is powered by either the VDD2H (e.g., 1.05V) or VDD2L (e.g., 0.9V) voltage rail when DVFSC mode is enabled. | ¶¶68-69 | col. 6:1-6 |
| a peripheral circuit electrically connected to the DRAM core cell, wherein the peripheral circuit is supplied with a second voltage... wherein the second voltage is lower than 1.1V | Buffers and data path circuits within the LPDDR5 DRAM module, which are also supplied by the VDD2H or VDD2L rails, both of which are typically below 1.1V. A diagram from a JEDEC workshop illustrates the distinct power rails for "Core" and "Peri" (peripheral) circuits. (Compl. p. 33). | ¶70 | col. 6:7-11 |
| wherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell | The complaint alleges on information and belief that the core cells and peripheral circuits of the LPDDR5 DRAM are formed on a single chip module, with the peripheral circuits being external to the core cells themselves. | ¶71 | col. 6:11-14 |
| wherein the first voltage and the second voltage are capable of making the DRAM be applied to an embedded display port (eDP) | The complaint alleges on information and belief that the LPDDR5 DRAM module may be applied to an eDP and that accused Lenovo devices utilize an eDP protocol. | ¶72 | col. 6:15-17 |
- Identified Points of Contention:
- Scope Questions: The construction of "external to the DRAM core cell" will be critical. The parties may dispute whether circuits integrated onto the same monolithic piece of silicon can be considered "external" to one another in the manner required by the claim.
- Technical Questions: What evidence does the complaint provide that the low-voltage operation of the main system LPDDR5 DRAM is specifically what makes it "capable of [being] applied to an embedded display port," as opposed to other design features? The complaint makes this allegation on "information and belief," suggesting it may be an area requiring further factual development.
V. Key Claim Terms for Construction
For the ’834 Patent:
- The Term: "programmable transmitting or receiving data rate, a... programmable transmitting or receiving signal swing"
- Context and Importance: The infringement theory for the '834 Patent hinges on this term. The case may turn on whether the accused LPDDR5 memory's standardized DVFS feature, which dynamically adjusts frequency and voltage for power management, satisfies the claim's requirement of being "programmable... corresponding to firmware or software." Practitioners may focus on this term because it draws a distinction between inherent, automatic operation and deliberate reconfigurability.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification does not narrowly define "programmable," stating that programmability can be associated with "firmware or software included in the ASIC processor." (’834 Patent, col. 2:13-15). This could be argued to encompass any parameter that can be changed by software, including power management routines.
- Evidence for a Narrower Interpretation: The overall context of the invention as a "reconfigurable... memory platform" could support an interpretation that "programmable" refers to a more fundamental reconfiguration to adapt the module to different hardware standards, rather than the real-time operational adjustments of DVFS. (’834 Patent, Title).
For the ’017 Patent:
- The Term: "the peripheral circuit is external to the DRAM core cell"
- Context and Importance: This term is central to distinguishing the claimed invention from a standard integrated DRAM chip. The defendant may argue that on a modern, monolithic DRAM chip, all circuits are inherently internal to the device. The plaintiff's infringement case requires establishing that functionally distinct circuit blocks on the same chip can be considered "external" to one another.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's own Figure 1 depicts the "Memory core unit" and "Peripheral circuit unit" as separate, distinct blocks, which may support the interpretation that "external" refers to functional or architectural separation rather than physical separation onto different dies. (’017 Patent, FIG. 1).
- Evidence for a Narrower Interpretation: The claim itself states that the core cell and peripheral circuit "are formed on a single chip." (’017 Patent, col. 6:11-12). This language could be used to argue that elements on a single chip cannot, by definition, be "external" to one another.
VI. Other Allegations
Indirect Infringement
- The complaint alleges inducement of infringement, stating that Lenovo provides "instructions, documentation, technical support, marketing, product manuals, advertisements, and online documentation" that urge customers to use the accused products in an infringing manner. (Compl. ¶¶60, 74). It also pleads contributory infringement, alleging the accused components are material to the invention and have no substantial non-infringing uses. (Compl. ¶¶61, 75).
Willful Infringement
- The complaint alleges willful infringement based on two theories. First, it alleges pre-suit knowledge or willful blindness, asserting that Lenovo, as a major technology company, "regularly monitors memory module technology advances" and deliberately avoided learning of Plaintiff's patents. (Compl. ¶42). Second, it asserts that the filing of the lawsuit provides Defendants with actual knowledge, making any continued infringement post-filing willful. (Compl. ¶43).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "programmable" in the ’834 Patent, which suggests deliberate reconfigurability, be construed to cover the standardized, dynamic power-management adjustments (DVFS) inherent in the accused LPDDR5 memory technology?
- A central claim construction dispute for the ’017 patent family will concern the term "external to the DRAM core cell." The case may turn on whether functionally distinct circuits integrated onto a single monolithic silicon chip can be considered "external" to one another as required by the claims.
- A key evidentiary question will be one of functional linkage: what proof can Plaintiff offer to connect the specific low-voltage operation of the accused system DRAM to the capability of being "applied to an embedded display port," as required by the ’017 Patent, beyond the general assertion made on information and belief in the complaint?