DCT
2:25-cv-01040
Wecrevention Inc v. Dell Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: WeCrevention, Inc. (Texas)
- Defendant: Dell Inc. and Dell Technologies, Inc. (Delaware)
- Plaintiff’s Counsel: Fabricant LLP
- Case Identification: 2:25-cv-01040, E.D. Tex., 10/10/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas based on several theories, including Defendant's operation of a "Dell Secure Area" within a partner facility, a comprehensive work-from-home policy for employees residing in the district, the physical presence of Dell-authorized partners and resellers, and Dell's provision of managed IT services to customers located in the district.
- Core Dispute: Plaintiff alleges that Defendant’s laptops and other electronic devices incorporating LPDDR5 and LPDDR5x DRAM infringe five patents related to reconfigurable memory module architectures and low-voltage power management for dynamic random access memory (DRAM).
- Technical Context: The patents address high-speed computer memory architecture, focusing on methods for improving power efficiency and performance through reconfigurable data buses and low-voltage operation, which are critical technologies in battery-powered consumer electronics.
- Key Procedural History: The complaint asserts that Defendant has previously admitted or not contested personal jurisdiction in the Eastern District of Texas in prior, unrelated lawsuits.
Case Timeline
| Date | Event |
|---|---|
| 2011-10-11 | ’942 Patent Priority Date |
| 2011-11-03 | ’834 Patent Priority Date |
| 2012-07-17 | ’017, ’098, and ’652 Patents Priority Date |
| 2015-10-20 | ’942 Patent Issued |
| 2015-12-01 | ’834 Patent Issued |
| 2019-09-01 | Alleged period of infringement begins (products with LPDDR5 DRAM) |
| 2021-05-04 | ’017 Patent Issued |
| 2024-02-06 | ’098 Patent Issued |
| 2024-11-26 | ’652 Patent Issued |
| 2025-10-10 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,201,834 - "Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module"
The Invention Explained
- Problem Addressed: The patent background describes the inefficiencies that arise when memory modules, which are often based on rigid industry standards, are integrated with logic units and processors from different semiconductor process generations. This mismatch can lead to suboptimal power consumption, data transmission efficiency, and noise interference (Compl. ¶28; ’834 Patent, col. 1:24-52).
- The Patented Solution: The invention proposes an electronics system with a reconfigurable memory architecture. It introduces a "logic unit" that mediates between a group of memory ICs and an "ASIC processor." The data bus between the memory and the logic unit ("first transmission bus") and the data bus between the logic unit and the processor ("second transmission bus") have programmable characteristics, such as data rate and signal swing. These characteristics can be adjusted via firmware or software on the processor, allowing the system to be optimized for different components or operating states (’834 Patent, Abstract; col. 2:4-22).
- Technical Importance: This reconfigurability allows a single memory subsystem design to be dynamically optimized for various processors or workloads, which may enhance performance and energy efficiency in complex electronic devices (’834 Patent, col. 2:23-42).
Key Claims at a Glance
- The complaint asserts independent claim 21 (Compl. ¶34).
- Claim 21 Essential Elements:
- An electronics system device with a reconfigurable high speed memory chip module, comprising:
- An application-specific integrated circuit (ASIC) processor;
- A memory cell array group comprising multiple memory cell array ICs;
- A first transmission bus coupled to the memory group, having a first programmable data rate and signal swing corresponding to firmware or software in the ASIC processor;
- A logic unit coupled to the first transmission bus for accessing the memory group; and
- A second transmission bus coupled between the logic unit and the ASIC processor, having a second programmable data rate and signal swing associated with the firmware or software in the ASIC processor.
- The complaint asserts "one or more claims," which suggests a reservation of the right to assert dependent claims (Compl. ¶33).
U.S. Patent No. 10,998,017 - "Dynamic random access memory applied to an embedded display port"
The Invention Explained
- Problem Addressed: The patent addresses the power consumption of DRAM when used as a frame buffer in display timing controllers that support panel self-refresh (PSR). While PSR saves power by allowing the main graphics processing unit (GPU) to turn off, the DRAM in the timing controller remains active and consumes power, which can limit the battery life of portable devices (’017 Patent, col. 1:23-46, 1:55-62).
- The Patented Solution: The invention claims a DRAM architecture specifically designed for low-power operation by using voltages below the 1.1V threshold. The solution separates the DRAM into a "DRAM core cell" and a "peripheral circuit," both of which are supplied with voltages lower than 1.1V. This design is intended to reduce power consumption when the DRAM is applied to an embedded display port (eDP) (’017 Patent, Abstract; col. 2:18-34).
- Technical Importance: By creating a DRAM optimized for low-voltage operation in an eDP context, the invention aims to mitigate the power overhead of advanced display features like PSR, thereby extending battery endurance in devices like laptops and tablets (’017 Patent, col. 2:26-34).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶50).
- Claim 1 Essential Elements:
- A dynamic random access memory (DRAM) comprising:
- A DRAM core cell supplied with a first voltage lower than 1.1V;
- A peripheral circuit electrically connected to the DRAM core cell, supplied with a second voltage lower than 1.1V;
- The DRAM core cell and peripheral circuit are formed on a single chip, with the peripheral circuit being external to the DRAM core cell;
- The first and second voltages are capable of making the DRAM be applied to an embedded display port (eDP).
- The complaint asserts "one or more claims," suggesting a reservation of the right to assert dependent claims (Compl. ¶49).
U.S. Patent No. 11,894,098 - "Dynamic random access memory applied to an embedded display port"
- Technology Synopsis: Continuing from the technology in the ’017 Patent, this patent claims a low-voltage DRAM architecture. It specifies that the voltage supplied to the DRAM core cell is different from the voltage supplied to the peripheral circuit, with both voltages remaining below 1.1V, to reduce power consumption (Compl. ¶64; ’098 Patent, Abstract).
- Asserted Claims: The complaint asserts at least claim 1 (Compl. ¶64).
- Accused Features: The accused LPDDR5 DRAM modules allegedly use different voltage rails (VDD2H for the core and VDD2L for the peripheral circuit) during low-power operation, meeting the claim limitations (Compl. ¶¶66-69).
U.S. Patent No. 12,154,652 - "Dynamic random access memory applied to an embedded display port"
- Technology Synopsis: Also related to the ’017 Patent, this patent claims a low-voltage DRAM architecture separating the "DRAM core cell" from an "input/output circuit." It requires the voltage for the core ("first voltage") to be different from the voltage for the I/O circuit ("third voltage"), with both operating below 1.1V, to achieve power savings (Compl. ¶77; ’652 Patent, Abstract).
- Asserted Claims: The complaint asserts at least claim 1 (Compl. ¶77).
- Accused Features: The accused LPDDR5 DRAM modules are alleged to use separate power rails for the DRAM core (e.g., VDD2H or VDD2L) and the I/O circuit (VDDQ), with the respective voltages being different and below the 1.1V threshold (Compl. ¶¶81-84).
U.S. Patent No. 9,164,942 - "High speed memory chip module and electronics system device with a high speed memory chip module"
- Technology Synopsis: Related to the ’834 Patent, this patent describes a memory system where a logic unit accesses data from memory ICs over a wide "first transmission bus." The logic unit then converts this "first set of parallel data" into a "second set of parallel data" with a different bit width and transmits it to an ASIC processor over a "second transmission bus," enabling efficient data transfer between disparate components (’942 Patent, col. 2:4-24).
- Asserted Claims: The complaint asserts at least claim 19 (Compl. ¶92).
- Accused Features: The complaint alleges that the Integrated Memory Controller (IMC) in the accused Intel processors acts as the logic unit. It allegedly accesses a wide (e.g., x128 dual channel) "first set of parallel data" from the LPDDR5 DRAM module and converts it to a "second set of parallel data" of a different width for use by the processor cores via an internal bus (Compl. ¶¶99-101).
III. The Accused Instrumentality
Product Identification
- Defendant's products manufactured since September 2019 that include LPDDR5 DRAM and LPDDR5x DRAM. The complaint identifies the Dell XPS, Dell Plus, Latitude, and Precision product lines as examples, and uses the Dell XPS 13 Plus 9320 laptop as a representative accused product (Compl. ¶¶28, 35).
Functionality and Market Context
- The accused products are consumer and professional electronic devices, primarily laptops. The infringement allegations focus on the technical operation of the processor (identified as an Intel "Alder Lake" series processor) and its interaction with the LPDDR5 DRAM module (Compl. ¶¶36-37). Key alleged functionalities include the processor's Integrated Memory Controller (IMC), which manages data flow on the memory bus, and an internal "ring interconnect" that links the processor cores to the IMC. The complaint alleges these components utilize Dynamic Voltage and Frequency Scaling (DVFS) and various power-saving states (C-States) to manage performance and energy consumption, which Plaintiff contends practices the patented inventions (Compl. ¶¶38, 42, 52). A diagram provided in the complaint shows how an Intel Alder Lake processor's interconnect links the processing cores with the integrated memory controller. (Compl. p. 19).
IV. Analysis of Infringement Allegations
’834 Patent Infringement Allegations
| Claim Element (from Independent Claim 21) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an application-specific integrated circuit (ASIC) processor | The Intel Core i7 "Alder Lake" processor in the Dell XPS 13 Plus 9320. | ¶36 | col. 2:6 |
| a type of memory cell array group...comprises multiple memory cell array ICs | The 16 GB LPDDR5 DRAM module. | ¶37 | col. 4:37-41 |
| a first transmission bus coupled to the type of memory cell array group having a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing corresponding to firmware or software comprised in the ASIC processor | The memory bus connecting the LPDDR5 DRAM module to the processor's IMC, which allegedly supports dynamic frequency and voltage scaling controlled by firmware in the Alder Lake processor. | ¶¶38-40 | col. 2:11-16 |
| a logic unit coupled to the first transmission bus for accessing the type of memory cell array group through the first transmission bus | The Integrated Memory Controller (IMC) within the Alder Lake processor. | ¶41 | col. 2:9-10 |
| a second transmission bus coupled between the logic unit and the ASIC processor having a second programmable...data rate, a second programmable...signal swing associated to the firmware or the software comprised in the ASIC processor | The ring interconnect within the Alder Lake processor, which connects the processor cores to the IMC and allegedly provides programmable data rate and voltage swing controlled by firmware. | ¶42 | col. 2:17-22 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the term "logic unit," which the patent figures depict as a discrete component between the memory and the processor, can be construed to read on an Integrated Memory Controller (IMC) that is part of the same silicon die as the "ASIC processor." Similarly, the claim requires the second bus to be "coupled between the logic unit and the ASIC processor," which raises a construction issue if the logic unit (IMC) is considered part of the ASIC processor.
- Technical Questions: What evidence does the complaint provide that the standard-compliant Dynamic Voltage and Frequency Scaling (DVFS) of the accused memory bus and the C-State power management of the processor's ring interconnect meet the claim limitations of being "programmable...corresponding to firmware or software"? The complaint cites to Intel datasheets to support this connection (Compl. ¶¶39, 42).
’017 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a DRAM core cell, wherein the DRAM core cell is supplied with a first voltage...lower than 1.1V | The core cells of the LPDDR5 DRAM, which are allegedly supplied by voltage rails (VDD2H or VDD2L) that operate below 1.1V (e.g., typical 1.05V or 0.9V) when DVFSC mode is enabled. | ¶¶52-53 | col. 6:1-4 |
| a peripheral circuit electrically connected to the DRAM core cell...supplied with a second voltage...lower than 1.1V | Buffers and data path circuits within the LPDDR5 DRAM module, which are also allegedly supplied by the VDD2H or VDD2L rails operating below 1.1V. | ¶54 | col. 6:5-9 |
| wherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell | The complaint alleges this architecture is typical for the accused LPDDR5 DRAM modules. | ¶55 | col. 6:11-14 |
| wherein the first voltage and the second voltage are capable of making the DRAM be applied to an embedded display port (eDP) | The accused Dell devices allegedly utilize an eDP protocol to communicate with their displays, and the LPDDR5 DRAM module may be applied to that port. | ¶56 | col. 6:15-17 |
- Identified Points of Contention:
- Scope Questions: The infringement analysis may turn on the definitions of "DRAM core cell" and "peripheral circuit" within the context of a modern LPDDR5 DRAM chip. The claim requires the peripheral circuit to be "external to" the core cell, making the precise boundary between these components a likely point of dispute. A diagram in the complaint distinguishes between "Core," "Peri," and "IO" sections of the DRAM, which may support Plaintiff's proposed construction (Compl. p. 25).
- Technical Questions: What is the required nexus for the voltages to be "capable of making the DRAM be applied to an eDP"? Does this require a specific functional link between the low-voltage operation and the eDP application, as the patent's background suggests, or is it sufficient that a device simply contains both a low-voltage-capable DRAM and an eDP?
V. Key Claim Terms for Construction
For the ’834 and ’942 Patents
- The Term: "logic unit"
- Context and Importance: This term's construction is central to the infringement theory. Defendant may argue that the accused Integrated Memory Controller (IMC) is an integral part of the "ASIC processor," not a separate "logic unit" as contemplated by the patent. The claim structure requires the logic unit to be coupled between the memory bus and the ASIC processor, making its definition critical.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the function of the logic unit as "accessing the type of memory cell array group through a first transmission bus" (’834 Patent, col. 2:9-11), a primary function of an IMC. This functional description may support reading the claim on an integrated component.
- Evidence for a Narrower Interpretation: The patent's figures consistently depict the "logic unit" (106) as a structurally separate block from the "ASIC processor" (112) (’834 Patent, Fig. 1). The specification also discusses the benefits of using different semiconductor processes for the logic unit and the processor, which suggests they are conceived as distinct entities (’834 Patent, col. 5:48-67).
For the ’017, ’098, and ’652 Patents
- The Term: "peripheral circuit"
- Context and Importance: The claims of the ’017 patent family rely on a distinction between the "DRAM core cell" and the "peripheral circuit." The claim requires the peripheral circuit to be "external to" the core cell and, in the case of the ’098 Patent, to be supplied by a different voltage. The precise technical scope of what constitutes a "peripheral circuit" in a modern DRAM chip will be a key issue.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification does not provide an explicit definition for "peripheral circuit," which may suggest the term should be given its plain and ordinary meaning to one of skill in the art, potentially supported by extrinsic evidence like the JEDEC standards cited in the complaint (Compl. ¶¶54-55).
- Evidence for a Narrower Interpretation: The patent’s sole figure is a block diagram that explicitly separates the "Memory core unit" (102) from the "Peripheral circuit unit" (104) (’017 Patent, Fig. 1). This visual separation may support an argument that the patent contemplates structurally or functionally distinct sections of the DRAM die, not merely different types of transistors intermingled within the same functional block.
VI. Other Allegations
- Indirect Infringement: For all asserted patents, the complaint alleges induced infringement. The allegations are based on Defendant's affirmative acts of selling the Accused Products and providing instructions, product manuals, and technical support that allegedly encourage and facilitate direct infringement by end-users (e.g., Compl. ¶¶43-44, 57-58). Contributory infringement is also alleged on the basis that the accused components are material to the inventions and not staple articles of commerce (e.g., Compl. ¶45, 59).
- Willful Infringement: The complaint alleges willful infringement based on both pre- and post-suit knowledge. It alleges that Defendant, as a sophisticated technology company, "regularly monitors memory technology advances" and was therefore either aware of the patents or was willfully blind to its infringement prior to the suit (Compl. ¶29). Knowledge as of the filing of the lawsuit is asserted as the basis for ongoing willful infringement (Compl. ¶30).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "logic unit," which is depicted in the ’834 and ’942 patents as a discrete architectural block, be construed to cover an "Integrated Memory Controller" that resides on the same silicon die as the main processor? The case may turn on whether the claimed architecture is defined by function or by physical separation.
- A second central question will be one of component mapping: how are the claim terms "DRAM core cell," "peripheral circuit," and "input/output circuit" from the ’017 patent family to be defined and demarcated within the architecture of a modern LPDDR5 memory chip? The infringement analysis will depend heavily on the technical evidence distinguishing these internal chip regions and their respective power supplies.
- A key evidentiary question will be one of functional nexus: does the accused products' use of industry-standard technologies like DVFS and eDP constitute infringement of claims that appear to be directed at bespoke, reconfigurable, or specially-applied memory systems, or is there a fundamental mismatch between the general-purpose nature of the accused functionality and the specific solutions described in the patents?