DCT

2:25-cv-01160

Monolithic 3D Inc v. Kioxia Corp

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-01160, E.D. Tex., 11/26/2025
  • Venue Allegations: Venue is alleged to be proper under 28 U.S.C. § 1391(c) because the Defendant is a foreign corporation, which may be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s 3D NAND semiconductor memory products, and the methods for making them, infringe a portfolio of eight U.S. patents relating to three-dimensional integrated circuit structures and fabrication processes.
  • Technical Context: The lawsuit concerns 3D NAND flash memory, a technology that enables high-density data storage by stacking memory cells vertically, and which is foundational to modern solid-state drives (SSDs), smartphones, and data center storage.
  • Key Procedural History: The complaint does not mention any prior litigation, licensing history, or post-grant proceedings involving the patents-in-suit and the named parties.

Case Timeline

Date Event
2010-10-11 Earliest Priority Date for '473 and '737 Patents
2010-11-18 Earliest Priority Date for '214, '802, '396, and '503 Patents
2012-04-09 Earliest Priority Date for '181 Patent
2016-10-10 Earliest Priority Date for '240 Patent
2022-05-24 U.S. Patent No. 11,342,214 Issued
2022-10-18 U.S. Patent No. 11,476,181 Issued
2023-02-28 U.S. Patent No. 11,594,473 Issued
2023-03-21 U.S. Patent No. 11,610,802 Issued
2023-04-04 U.S. Patent No. 11,621,240 Issued
2023-10-31 U.S. Patent No. 11,804,396 Issued
2024-01-02 U.S. Patent No. 11,862,503 Issued
2025-02-11 U.S. Patent No. 12,225,737 Issued
2025-10-13 Defendant allegedly attended One Compute Project Global Summit
2025-11-26 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,342,214 - "Methods for Producing a 3D Semiconductor Memory Device and Structure"

The Invention Explained

  • Problem Addressed: The patent addresses the general field of Integrated Circuit (IC) devices and fabrication methods, with a particular focus on Three Dimensional Integrated Circuit (3D IC) devices (Compl. ¶20; ’214 Patent, col. 1:49-53). The background implicitly addresses the challenge of increasing semiconductor device density and performance, which 3D stacking seeks to solve.
  • The Patented Solution: The invention describes a method for creating a 3D memory device by fabricating multiple levels of memory cells on top of a foundational "first level" that contains transistors formed in a single crystal layer (’214 Patent, Abstract). The method involves forming the first level with transistors and metal layers, then forming a second level and a third level above it, and subsequently performing etch and processing steps to create memory transistors within these upper levels (’214 Patent, col. 2:1-24). This approach is enabled by layer transfer technologies that allow high-quality crystalline layers to be stacked (’214 Patent, col. 10:1-16).
  • Technical Importance: This approach suggests a method for monolithic 3D integration, aiming to achieve higher device density, improved performance, and lower power consumption by reducing the length of interconnects between logic and memory components (’214 Patent, col. 2:2-11).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶37).
  • The essential elements of independent claim 1, a method claim, include:
    • Providing a first level that comprises a first single crystal layer.
    • Forming a plurality of first transistors with single crystal channels within this first level.
    • Forming first and second metal layers, with the first level comprising the transistors and these metal layers.
    • Forming at least one second level above the second metal layer.
    • Performing a first etch step to create first holes in the second level.
    • Forming at least one third level above the second level.
    • Performing a second etch step to create second holes in the third level.
    • Performing additional processing to form a plurality of memory cells (with first memory transistors) in the second level and a plurality of memory cells (with second memory transistors) in the third level.

U.S. Patent No. 11,476,181 - "3D Semiconductor Device and Structure with Metal Layers"

The Invention Explained

  • Problem Addressed: The patent describes the benefits of 3D ICs, such as shorter interconnects and higher performance, while noting the limitations of prior art approaches, including the limited density of Through Silicon Vias (TSVs) and challenges with handling thinned wafers (’181 Patent, col. 2:2-29).
  • The Patented Solution: The invention is a 3D semiconductor device structure, rather than a method. It comprises a "first level" containing transistors made from a single crystal silicon layer, overlaid by multiple metal layers (’181 Patent, Abstract). A "second level" containing a plurality of second transistors is stacked on top. A key feature is a "connective path," such as a via with specific dimensions (less than 500 nm diameter), that passes through the second level to connect upper metal layers to lower ones (’181 Patent, Abstract). The structure also specifies vertically oriented transistors in the second level and a power/ground connection to the third metal layer.
  • Technical Importance: This claimed structure provides a specific architectural template for a monolithically integrated 3D device, aiming to realize the density and performance advantages of vertical stacking while defining specific structural relationships between the logic and memory layers (’181 Patent, col. 2:2-11).

Key Claims at a Glance

  • The complaint asserts at least independent claim 4 (Compl. ¶54).
  • The essential elements of independent claim 4, a device claim, include:
    • A first level comprising a single crystal silicon layer and a plurality of first transistors with single crystal channels.
    • A first metal layer overlaying the first transistors.
    • A second metal layer overlaying the first metal layer.
    • A third metal layer overlaying the second metal layer.
    • A second level overlaying the first level, comprising a plurality of second transistors.
    • A fourth metal layer overlaying the second level.
    • A connective path (via) between the fourth metal layer and the third or second metal layers, disposed through the second level, with a diameter between 5 nm and 500 nm.
    • At least one of the second transistors is vertically oriented.
    • The third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

U.S. Patent No. 11,594,473 - "3D Semiconductor Device and Structure with Metal Layers and a Connective Path"

  • Technology Synopsis: The patent describes a 3D semiconductor device structure with stacked levels of transistors and metal layers. The invention focuses on the physical arrangement, including a connective via of specific dimensions and the inclusion of a metal gate on at least one of the upper-level transistors, with the uppermost metal layer forming part of an overall chip power-grid (’473 Patent, Abstract).
  • Asserted Claims: At least independent claim 13 is asserted (Compl. ¶73).
  • Accused Features: The complaint alleges that KIOXIA’s BiCS8 3D flash memory products embody this structure, pointing to the stacked CMOS-on-array design, the multiple metal interconnect layers, the vertical vias connecting layers, and the use of metal gates for the NAND transistors (Compl. ¶¶74-82).

U.S. Patent No. 11,610,802 - "Method For Producing A 3D Semiconductor Device and Structure with Single Crystal Transistors and Metal Gate Electrodes"

  • Technology Synopsis: This patent claims a method for producing a 3D device. The process involves forming peripheral circuitry on a first level, building second and third levels above it through layer transfers, and then performing lithography and processing steps to create memory cells. A key step is simultaneously depositing metal gate electrodes for transistors on both the second and third levels (’802 Patent, Abstract).
  • Asserted Claims: At least independent claim 8 is asserted (Compl. ¶93).
  • Accused Features: The accused process is the manufacturing of KIOXIA’s BiCS8 memory, which allegedly involves forming a CMOS peripheral layer, stacking two NAND decks above it, and using lithography and deposition processes to simultaneously form the memory cell gate electrodes in both decks (Compl. ¶¶94-102).

U.S. Patent No. 11,804,396 - "Methods for Producing A 3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers"

  • Technology Synopsis: The patent claims a method for producing a 3D device similar to the ’802 Patent, involving stacked levels and simultaneous gate deposition. This patent adds the limitation of forming "at least four independent memory arrays" from the memory cells created in the stacked levels (’396 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 is asserted (Compl. ¶111).
  • Accused Features: The complaint alleges that KIOXIA’s BiCS8 memory is made by the claimed process and that the final die comprises at least four independent memory arrays, as shown in a provided die photograph (Compl. ¶121; p. 66).

U.S. Patent No. 11,862,503 - "Method for Producing a 3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers"

  • Technology Synopsis: The technology claimed is a manufacturing method for a 3D semiconductor device. The process involves providing a first level, forming multiple metal and memory levels above it, and performing lithography and processing steps. A key feature is a deposition step that "simultaneously deposits gate electrodes" for second and third transistors located on different vertical levels (’503 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 is asserted (Compl. ¶130).
  • Accused Features: The complaint alleges that the manufacturing process for KIOXIA’s BiCS8 memory, which involves stacking two NAND decks and using a single process to form the gate electrodes for both, infringes this method patent (Compl. ¶¶131-137).

U.S. Patent No. 11,621,240 - "3D Memory Devices and Structures With Control Circuits"

  • Technology Synopsis: This patent describes a 3D device structure comprising a "first level" with control circuits bonded to a "memory level" with an array of memory cells. The bond itself is a key feature, comprising both oxide-to-oxide and metal-to-metal bonding regions, with at least one memory cell disposed directly above a metal-to-metal bonding region (’240 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 is asserted (Compl. ¶146).
  • Accused Features: The accused product is KIOXIA’s BiCS8 memory, which allegedly features a CMOS control circuit layer bonded to a 3D NAND memory array using a hybrid bonding technique that includes both oxide and metal bonding regions (Compl. ¶¶147, 151-152).

U.S. Patent No. 12,225,737 - "Method for Producing 3D Semiconductor Devices And Structures With Transistors And Memory Cells"

  • Technology Synopsis: The patent claims a method for producing a 3D device by forming memory control circuits on a first level, stacking second and third levels above it, and forming memory cells. A key claimed step is "performing bonding of said first level to said second level, wherein said bonding comprises oxide to oxide bonding" (’737 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 is asserted (Compl. ¶163).
  • Accused Features: The complaint alleges KIOXIA’s BiCS8 memory is manufactured using a process that includes bonding the CMOS control circuit layer to the stacked memory array layers via an oxide-to-oxide bond (Compl. ¶¶164, 172).

III. The Accused Instrumentality

Product Identification

The complaint identifies the Accused Products as encompassing "all KIOXIA 3D NAND memory," including all KIOXIA SSD products (such as the CM, PM, RM, FL, CD, XD, BG, and XG Series) and all 3D Flash Memory products, such as those marketed under the "BiCS Flash" brand (Compl. ¶¶32, 36). A specific exemplary product identified is the "Kioxia part number T2BIGB5A2V comprising BiCS8 3D BiCs Flash memory" (Compl. ¶36).

Functionality and Market Context

The complaint alleges the Accused Products are 3D NAND flash memory integrated circuits that provide essential data storage for a wide array of modern electronics, including smart phones, servers, computers, and automobiles (Compl. ¶¶13, 47). The technical functionality, as depicted in scanning electron microscope (SEM) images provided in the complaint, involves a "CMOS Bonded to Array" (CBA) architecture (Compl. p. 12). This architecture consists of a base layer of CMOS peripheral control circuits ("a first level") bonded to one or more vertically stacked decks of 3D NAND memory arrays ("at least one second level") (Compl. ¶¶38-39). A photograph of an SSD product labeled "MP700 ELITE" is provided as a representative example of a product incorporating the accused memory (Compl. ¶36; p. 9).

IV. Analysis of Infringement Allegations

U.S. Patent No. 11,342,214 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a method... comprising: providing a first level comprising a first single crystal layer; forming a plurality of first transistors each comprising a single crystal channel The process of manufacturing the BiCS8 3D BiCs Flash memory, which provides a first level containing CMOS peripheral circuits comprising single crystal silicon transistors. A provided SEM cross-section shows a "CMOS Bonded to Array" layer labeled as "a first level" and "a plurality of first transistors." ¶38 col. 13:45-56
forming a first metal layer and a second metal layer, wherein said first level comprises said plurality of first transistors, said first metal layer, and said second metal layer The manufacturing process includes forming at least a first and second metal layer within the CMOS first level to interconnect the transistors. An SEM image identifies these metal layers below the 3D NAND array. ¶39 col. 8:59-67
forming at least one second level disposed above said second metal layer The process forms "3D NAND Deck 1" as a second level vertically stacked above the metal layers of the CMOS first level. ¶39 col. 2:12-13
performing a first etch step comprising etching first holes within said second level After patterning, memory tube holes are etched within the layers of NAND Deck 1 to create the vertical channels for the memory cells. A diagram illustrates the "Memory Tube Opening" and its constituent parts. ¶40 col. 2:14-15
forming at least one third level above said at least one second level The process forms "3D NAND Deck 2" as a third level stacked on top of NAND Deck 1. ¶41 col. 2:16-17
performing a second etch step comprising etching second holes within said third level The process of etching the vertical memory tube in NAND Deck 2 is alleged to be identical to the process used for NAND Deck 1. ¶42 col. 2:18-19
performing additional processing steps to form a plurality of first memory cells within said second level ... wherein said first memory cells each comprise one first memory transistor, and ... a plurality of second memory cells within said third level, wherein said second memory cells each comprise one second memory transistor An identical lithography, etching, and deposition process is allegedly used to form the vertical memory transistors in both Deck 1 and Deck 2. SEM images purport to show a "one first memory transistor" and "one second memory transistor." ¶¶43-45 col. 2:20-24

U.S. Patent No. 11,476,181 Infringement Allegations

Claim Element (from Independent Claim 4) Alleged Infringing Functionality Complaint Citation Patent Citation
a first level comprising a single crystal silicon layer and a plurality of first transistors, said plurality of first transistors each comprising a single crystal channel The accused BiCS8 device comprises a first level containing CMOS peripheral circuits, which are formed in a single crystal silicon substrate. ¶55 col. 1:58-61
a first metal layer overlaying said plurality of first transistors; a second metal layer overlaying said first metal layer; a third metal layer overlaying said second metal layer The device contains at least three metal layers within the first (CMOS) level, with the third metal layer alleged to be the bitline level. An SEM image labels these distinct metal layers. ¶56 col. 2:1-4
a second level, wherein said second level overlays said first level, wherein said second level comprises a plurality of second transistors The device’s 3D NAND array (containing multiple decks) constitutes the second level, which overlays the first (CMOS) level and comprises a plurality of memory cell transistors. ¶57 col. 2:5-7
a fourth metal layer overlaying said second level The device includes a fourth metal layer, which is used for external connection to the 3D NAND via bond wires. ¶58 col. 2:8-9
a connective path between said fourth metal layer and said third metal layer or said second metal layer, wherein said connective path comprises a via disposed through said second level, wherein said via has a diameter of less than 500 nm and greater than 5 nm The device contains vertical vias that connect the fourth metal layer to lower metal layers. An SEM image shows a via with a measured width of 170nm, which is within the claimed range. ¶¶59-61 col. 2:10-15
wherein at least one of said plurality of second transistors is vertically oriented The memory transistors within the 3D NAND array are vertically oriented channel devices. A provided diagram illustrates the vertical orientation of the polysilicon NAND tube channel. ¶62 col. 14:45-51
wherein said third metal layer is connected to provide a power or a ground signal to at least one of said plurality of second transistors The third metal layer, identified as the bitline, allegedly provides voltage signals to the 3D NAND memory transistors. ¶63 col. 2:18-21

Identified Points of Contention

  • Scope Questions: The asserted patents claim specific multi-level structures and multi-step fabrication methods. A potential point of contention is whether the terminology used in the claims, such as "first level," "second level," and "third level," can be unambiguously mapped to the integrated structure of the accused "CMOS Bonded to Array" device, which consists of a CMOS logic layer and two distinct "3D NAND Decks." For method patents like the ’214 Patent, a question may arise as to whether the sequence of steps performed by KIOXIA matches the precise sequence recited in the claims.
  • Technical Questions: The infringement allegations rely heavily on the Plaintiff's interpretation of SEM images. A technical question is whether the structures identified and labeled in the complaint’s figures (e.g., "a first metal layer," "a via") are technically accurate and perform the functions required by the claims. For the ’181 Patent, a question is whether the layer identified as the "third metal layer" is, in fact, "connected to provide a power or a ground signal" to the transistors, or if its function is more accurately described merely as data transmission (bitline), which may or may not fall within the claim's scope as construed by the court.

V. Key Claim Terms for Construction

U.S. Patent No. 11,342,214 (Claim 1)

  • The Term: "performing additional processing steps to form a plurality of first memory cells... and a plurality of second memory cells"
  • Context and Importance: This term is central to the method claim, which requires forming two distinct pluralities of memory cells in two different levels ("second" and "third"). The complaint alleges this corresponds to the creation of transistors in "Deck 1" and "Deck 2" of the accused device (Compl. ¶¶43-45). The construction of whether KIOXIA's integrated deck fabrication constitutes forming two distinct pluralities of cells via separate "additional processing steps" will be critical.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself is general, referring to "additional processing steps" without specifying they must be entirely separate manufacturing sequences. This may support an interpretation where patterning and etching different vertical sections of a single monolithic structure satisfies the limitation.
    • Evidence for a Narrower Interpretation: The patent’s structure, which separately introduces the formation of a "second level" and then a "third level," followed by distinct etch steps for each, may suggest that the "additional processing steps" for each plurality of memory cells are intended to be temporally or sequentially distinct processes rather than parts of a single, continuous fabrication flow for a multi-deck structure (’214 Patent, col. 2:12-24).

U.S. Patent No. 11,476,181 (Claim 4)

  • The Term: "a second level... comprises a plurality of second transistors"
  • Context and Importance: This term defines the upper, memory-containing portion of the device. The complaint alleges the "second level" in the accused product is the entire 3D NAND array, which includes both "Deck 1" and "Deck 2" (Compl. ¶57, p. 23). Practitioners may focus on whether a structure composed of two distinct, stacked "decks" can be considered a single "second level" as contemplated by the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract describes the second level simply as one that "overlays the first level and includes a plurality of second transistors," without limiting it to a single monolithic block. This language could support reading the term on a multi-deck stack that collectively overlays the first (CMOS) level.
    • Evidence for a Narrower Interpretation: The patent’s summary consistently refers to "a second level" in the singular, and the associated figures (e.g., Fig. 1) depict it as a single, contiguous layer of circuitry built upon a lower level. This could support an argument that the term requires a single, integrated level, raising a question of whether a structure explicitly manufactured as two separate "decks" meets this limitation.

VI. Other Allegations

Indirect Infringement

The complaint alleges both induced and contributory infringement for several patents, including the ’181, ’473, and ’240 Patents. The allegations for inducement are based on Defendant’s alleged affirmative acts of manufacturing and selling the Accused Products while providing instructions, technical support, and marketing materials that encourage customers and end-users to use the products in an infringing manner (Compl. ¶¶65, 84, 154). The allegations for contributory infringement are based on the assertion that the accused components are not staple articles of commerce and have no substantial non-infringing uses (Compl. ¶¶66, 85, 155).

Willful Infringement

The complaint alleges willful infringement for all asserted patents. The basis for willfulness is an allegation "upon information and belief" that KIOXIA has known of MonolithIC 3D's patents, including the specific patents-in-suit, prior to the lawsuit (Compl. ¶¶48, 67, 87, 105, 124, 140, 157, 175). The complaint also establishes knowledge as of the filing date of the complaint, which may support a claim for post-filing willfulness (Compl. ¶33).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A key evidentiary question will be one of structural and functional correspondence: does the extensive visual evidence provided by the Plaintiff, primarily consisting of SEM cross-sections, accurately depict the accused products' construction and conclusively demonstrate that features like the various metal layers and "connective paths" perform the exact functions and meet the specific structural and dimensional limitations required by the asserted device claims?
  • A core issue will be one of process mapping: can the multi-step manufacturing processes recited in the asserted method patents be mapped, in the correct sequence and with the required specificity, onto KIOXIA's integrated and proprietary BiCS FLASH fabrication flow, particularly with respect to steps alleged to occur "simultaneously" across different vertical decks?
  • A central question of claim construction will be the scope of foundational terms: how will the court construe terms such as "first level," "second level," and "third level" in the context of a "CMOS Bonded to Array" architecture, and does a structure built as two distinct "NAND decks" constitute one or two "levels" within the meaning of the patents?