DCT
2:25-cv-01170
Palisade Tech LLP v. Yangtze Memory Tech Co Ltd
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Palisade Technologies, LLP (Nevada)
- Defendant: Yangtze Memory Technologies Company, Ltd. (China)
- Plaintiff’s Counsel: Nelson Bumgardner Conroy PC
- Case Identification: 2:25-cv-01170, E.D. Tex., 11/26/2025
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign entity. The complaint further supports venue and personal jurisdiction by alleging Defendant has substantial business in Texas, places products into the stream of commerce with the knowledge they will be sold in the district, and has purposefully availed itself of the forum by previously filing its own patent infringement lawsuits in the Eastern District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s 3D NAND flash memory devices infringe five U.S. patents related to semiconductor memory architecture, operational methods, and manufacturing processes.
- Technical Context: The technology at issue is 3D NAND flash memory, a key component enabling high-density data storage in modern electronics, from mobile devices and consumer products to enterprise servers and data centers.
- Key Procedural History: The complaint makes several references to Defendant’s own patent litigation against Micron Technology, Inc. in the same judicial district to support its arguments for personal jurisdiction and venue. No prior litigation, licensing history, or post-grant proceedings involving the asserted patents are mentioned in the complaint.
Case Timeline
| Date | Event |
|---|---|
| 2007-01-31 | ’329 Patent Priority Date |
| 2010-04-13 | ’329 Patent Issue Date |
| 2010-09-30 | ’853 Patent Priority Date |
| 2013-05-14 | ’853 Patent Issue Date |
| 2014-05-08 | ’838 Patent Priority Date |
| 2014-10-10 | ’314 Patent Priority Date |
| 2015-03-31 | ’838 Patent Issue Date |
| 2015-07-22 | ’974 Patent Priority Date |
| 2016-03-08 | ’314 Patent Issue Date |
| 2016-12-20 | ’974 Patent Issue Date |
| 2025-10-06 | Defendant YMTC files suit against Micron in E.D. Tex. |
| 2025-11-26 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,697,329 - "Methods and Apparatus for Using a Configuration Array Similar to an Associated Data Array"
The Invention Explained
- Problem Addressed: The patent addresses potential manufacturing and reliability issues that arise when the physical layout of a memory chip’s main data array differs significantly from the layout of its smaller, associated configuration arrays, which store critical operational parameters (’329 Patent, col. 4:18-36). Different layouts can cause the arrays to react differently to manufacturing process variations, potentially compromising the reliability of the configuration data (’329 Patent, col. 6:56-col. 7:12).
- The Patented Solution: The invention proposes designing the configuration array to be "substantially similar" to the main data array in its physical layout. This includes disposing both arrays on the substrate in the same orientation, with wordlines and bitlines running in parallel directions, and using similar layouts for associated circuitry like drivers and vertical interconnects known as "zia" contacts (’329 Patent, Abstract; col. 5:1-12). This ensures that process adjustments affect both arrays similarly, improving yield and reliability (’329 Patent, col. 5:52-col. 6:12).
- Technical Importance: This design principle simplifies semiconductor manufacturing by promoting uniformity across different functional blocks on a die, leading to more predictable device performance and higher manufacturing yields.
Key Claims at a Glance
- The complaint asserts at least independent Claim 1 (Compl. ¶26).
- Essential elements of Claim 1 include:
- A memory comprising a substrate, a data array, and a separate configuration array for storing configuration information for the data array.
- The configuration array and the data array are disposed on the substrate in the same orientation relative to the substrate.
- The configuration array includes a plurality of "zia contact regions" disposed in "substantially similar relative locations" as a plurality of zia contact regions in the data array.
- The complaint expressly reserves the right to assert additional claims (Compl. ¶26, fn. 1).
U.S. Patent No. 8,441,853 - "Sensing for NAND Memory Based on Word Line Position"
The Invention Explained
- Problem Addressed: The patent describes a phenomenon in NAND flash memory known as the "back pattern effect," where a memory cell's programmed threshold voltage (Vth) is influenced by its physical position within a NAND string (’853 Patent, col. 3:10-24). Cells closer to the drain-side of the string are programmed after their source-side neighbors and experience different electrical conditions, which can lead to a wider and less predictable Vth distribution, making accurate data reads more challenging (’853 Patent, col. 3:10-24).
- The Patented Solution: The invention provides a method to compensate for these position-dependent effects by adjusting the "sensing process" based on the cell's location. The method involves assigning storage elements to different groups based on their position (e.g., source-side vs. drain-side) and applying a common sensing adjustment to all elements within a group (’853 Patent, Abstract). These adjustments can involve parameters like body bias, source voltage, or sensing time to tighten the Vth distributions for all cells, regardless of their position (’853 Patent, col. 4:31-42).
- Technical Importance: This technique improves the reliability of data retrieval in NAND flash, a critical factor for enabling higher-density multi-level cell (MLC) and triple-level cell (TLC) memories that rely on precise Vth control.
Key Claims at a Glance
- The complaint asserts at least independent Claim 1 (Compl. ¶44).
- Essential elements of Claim 1 (a method claim) include:
- Assigning each storage element in a NAND string to one of multiple groups of different sizes.
- A group closest to the source side has more storage elements than any other group.
- Connecting the NAND string at its drain side to a bit line and sensing circuitry.
- Sensing the threshold voltage of a selected element, where the "sensing is adjusted based on a position of the one group" to which the element is assigned.
- The complaint expressly reserves the right to assert additional claims.
U.S. Patent No. 8,996,838 - "Structure Variation Detection for a Memory Having a Three-Dimensional Memory Configuration"
- Technology Synopsis: The patent addresses physical imperfections in 3D memory structures, such as the "tapering" of vertical channels, which can affect cell performance at different layers (’838 Patent, col. 2:1-16). The invention discloses a method for detecting the location of such a structural variation and storing that location information, which the device can then access to apply different memory operation parameters (e.g., programming voltages, ECC schemes) to layers above and below the variation, thereby compensating for its effects (’838 Patent, Abstract).
- Asserted Claims: At least Claim 1 (Compl. ¶61).
- Accused Features: The complaint alleges that the accused 3D NAND products store and access information identifying a location of structural variation to "determine the finely tuned programming voltage" applied during operation (Compl. ¶63-64).
U.S. Patent No. 9,281,314 - "Non-Volatile Storage Having Oxide/Nitride Sidewall"
- Technology Synopsis: This patent describes a specific memory cell structure and manufacturing method intended to improve reliability. The invention forms a silicon oxide layer covering the sidewalls of both the charge storage region and the word line, but then forms a protective silicon nitride layer that covers only the oxide adjacent to the word line, leaving the oxide adjacent to the charge storage region exposed (’314 Patent, Abstract). This structure aims to prevent performance degradation caused by charge trapping in nitride near the sensitive charge storage region, while still protecting the word line during fabrication (’314 Patent, col. 2:1-6).
- Asserted Claims: At least Claim 13 (Compl. ¶76).
- Accused Features: The complaint alleges, based on Transmission Electron Microscope (TEM) images, that the method used to manufacture the accused 3D NAND products includes the claimed steps of forming specific oxide and nitride layers on the sidewalls of the charge storage regions and word lines (Compl. ¶77-81).
U.S. Patent No. 9,524,974 - "Alternating Sidewall Assisted Patterning"
- Technology Synopsis: The patent discloses an advanced semiconductor manufacturing method, a form of self-aligned double patterning (SADP), for creating extremely fine features. The process uses mandrels and sidewall spacers to define a pattern of trenches with two alternating cross-sectional profiles (’974 Patent, col. 2:9-25). For example, one set of trenches may be T-shaped (wider at the top), while the alternating set is rectangular. This structural difference allows for differential processing, such as filling one set of trenches with metal to form bit lines while creating insulating air gaps in the other set (’974 Patent, col. 2:40-54).
- Asserted Claims: At least Claim 17 (Compl. ¶93).
- Accused Features: The complaint alleges that YMTC uses an SADP process to manufacture the accused products, which it supports with analysis of bitline pitch and SEM images showing "cat ear like structures" indicative of removed mandrels (Compl. ¶96-97). The allegations map the inferred SADP steps to the elements of the asserted method claim (Compl. ¶94-100).
III. The Accused Instrumentality
Product Identification
- The complaint identifies Defendant’s semiconductor memory devices, specifically 3D NAND flash memory, as the accused instrumentalities (Compl. ¶2). An exemplary product is a KingSpec XG7000 solid-state drive, which a teardown allegedly revealed to contain 3D NAND memory manufactured by YMTC with package marking "YMN0ATF1B1HPAD" (Compl. ¶23-24).
Functionality and Market Context
- The accused products are non-volatile memory components used for data storage across a wide range of electronic devices, including mobile phones, computers, and data centers (Compl. ¶10). The complaint presents numerous die photographs, Scanning Electron Microscope (SEM) images, and TEM images to illustrate the physical structure of the accused products, including their vertically stacked layers, wordlines, bitlines, and zia contacts (Compl. p. 9, 13, 14, 19, 27, 34, 47). The complaint alleges Defendant is a "leader in 3D NAND flash" and holds a "leadership role in the NAND market" (Compl. ¶11).
IV. Analysis of Infringement Allegations
'329 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a data array; and a configuration array associated with, but separate from, the data array and adapted to store configuration information... | The accused products contain a main data array for user data and a separate configuration array that stores parameters for configuring the data array, such as those listed in Defendant's product datasheets. | ¶27-28 | col. 2:40-44 |
| wherein the configuration array and the data array are disposed on the substrate in a same orientation as each other relative to the substrate... | A die photograph of the accused product allegedly shows "only a single memory cell orientation," which is alleged to mean that both the data array and configuration array must share the same orientation of wordlines and bitlines. This die photograph shows annotated bitlines and wordlines in a uniform orientation. | ¶31 | col. 2:45-47 |
| and wherein the configuration array includes a plurality of zia contact regions that are disposed in substantially similar relative locations in the configuration array as a plurality of zia contact regions disposed in the data array. | An SEM image shows "zia structures" in the accused product. The complaint alleges that because the cell orientation is consistent throughout the device, the location and layout of these zia regions are necessarily the same for both the data array and the configuration array. | ¶32 | col. 2:47-50 |
- Identified Points of Contention:
- Evidentiary Questions: The complaint infers the existence and structure of a "configuration array" by citing Defendant's datasheets and patents, rather than direct analysis of the accused product's circuitry (Compl. ¶28-30). A potential point of contention is whether the accused products actually contain a separate configuration array that is physically distinct from the main data array as required by the claim.
- Scope Questions: The dispute may turn on the construction of "substantially similar relative locations." The complaint's argument rests on the premise that a uniform cell orientation across the die necessitates that the zia contact regions are in "substantially similar" locations in both arrays (Compl. ¶32). A defense may argue that this term requires a more specific geometric comparison of the layouts that the complaint does not provide.
'853 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| assigning each non-volatile storage element of the NAND string to a group among multiple groups... the multiple groups have different sizes... a group... which is closest to the source side has more non-volatile storage elements... | The accused products allegedly assign storage elements to a "source side deck" (128 wordlines) and a "drain side deck" (125 wordlines). The source side deck is closest to the common source plate and contains more elements. An annotated image from the complaint shows the source and drain side decks with their respective wordline counts. | ¶46-47 | col. 17:1-9 |
| sensing whether a threshold voltage of the selected non-volatile storage element is above a control gate voltage using the sensing circuitry, the sensing is adjusted based on a position of the one group in the NAND string. | The complaint alleges this adjustment is evidenced by the different deck sizes and by citing a separate YMTC patent ('671), which allegedly describes a process of setting different "maximum pass voltages" for word lines based on their position and vulnerability to "pass disturb." | ¶49 | col. 18:21-25 |
- Identified Points of Contention:
- Technical Questions: The complaint's primary evidence for the "sensing is adjusted" limitation is a reference to a separate YMTC patent that describes adjusting pass voltages applied to unselected wordlines during a program operation (Compl. ¶49). A key technical question will be whether adjusting pass voltages constitutes an adjustment to the "sensing" of the selected storage element's threshold voltage, as required by the claim.
- Scope Questions: The analysis will likely focus on whether the claim term "sensing is adjusted" can be construed to cover the adjustment of operating parameters (like pass voltages) that are not part of the direct measurement of the selected cell's conduction, or if it is limited to adjusting parameters within the sensing circuitry itself (e.g., pre-charge level, integration time).
V. Key Claim Terms for Construction
Patent: ’329 Patent
- The Term: "substantially similar relative locations"
- Context and Importance: This term is critical for determining infringement of Claim 1. Its definition will dictate the level of geometric precision required between the zia contact layouts in the data array and the alleged configuration array. Practitioners may focus on this term because the complaint's infringement theory relies on an inference from overall chip orientation rather than a direct comparison of two identified array layouts.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification suggests the purpose of the similar layout is functional—to ensure that process adjustments "will affect the arrays in the same way" and that they "perform similarly with regards to electrical characteristics" (’329 Patent, col. 5:10-17). This could support a construction based on functional impact rather than strict geometric identity.
- Evidence for a Narrower Interpretation: The detailed description discusses correcting for highly specific manufacturing defects like "optical proximity corrections (OPC)" and conductor narrowing, which are tied to precise geometric layouts (’329 Patent, col. 4:41-42; col. 6:56-62). This may support an argument that "substantially similar" requires near-identical placement to achieve the patent's stated goals.
Patent: ’853 Patent
- The Term: "sensing is adjusted"
- Context and Importance: The definition of this term is central to the infringement case for the ’853 patent, as the complaint’s evidence points to an adjustment of "pass voltages" rather than a direct adjustment of a sensing parameter like sense time or pre-charge level. Practitioners may focus on this term because it creates a potential mismatch between the patent's disclosure and the infringement allegation's evidence.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language states the "sensing is adjusted based on a position," which could be argued to encompass any position-based adjustment within the overall read or verify process that affects the outcome of the sensing operation.
- Evidence for a Narrower Interpretation: The patent's abstract and detailed description repeatedly list specific examples of sensing adjustments, such as "adjusting a sensing parameter such as body bias, source voltage, sensing time or sensing pre-charge level" (’853 Patent, Abstract; col. 4:34-38). This explicit list may be used to argue that the term "sensing is adjusted" is limited to these types of direct sensing circuit parameters and does not include pass voltages applied to unselected word lines.
VI. Other Allegations
- Indirect Infringement: For each of the five asserted patents, the complaint alleges induced infringement under 35 U.S.C. § 271(b). The allegations are based on Defendant allegedly encouraging infringement by its subsidiaries (such as YMTI), distributors, and customers through the creation and distribution of product datasheets, user manuals, technical support, and other instructional materials that promote the importation and use of the accused 3D NAND products in the United States (Compl. ¶33-34, 50-51, 65-66, 82-83, 101-102).
- Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for this allegation is Defendant's alleged continued infringement after having knowledge of the patents, with knowledge allegedly established from the date of service of the complaint (Compl. ¶35, 52, 67, 84, 103).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of evidentiary linkage: for patents concerning the internal operation of the memory ('329, '853, '838), the complaint relies on Defendant's other patents, datasheets, and public statements to allege how the accused products function. A key question for the court will be whether discovery and reverse engineering confirm that the accused products actually implement the specific structures and methods described in these extrinsic documents.
- A second central issue will be one of definitional scope: does the term "sensing is adjusted" in the ’853 patent, which the specification illustrates with examples like adjusting sense time and pre-charge level, read on the practice of adjusting pass voltages on unselected word lines, as alleged in the complaint?
- Finally, for the manufacturing-focused patents ('314 and '974), a key question will be one of process verification: can Plaintiff prove, through analysis of the final imported product, that Defendant’s proprietary manufacturing process used in China incorporates all steps of the asserted method claims, as required for infringement under 35 U.S.C. § 271(g)?