DCT

2:25-cv-01176

Monolithic 3D Inc v. SK Hynix Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-01176, E.D. Tex., 11/26/2025
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign company that may be sued in any judicial district and has committed acts of patent infringement and conducts business in the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s 3D NAND semiconductor memory products infringe eight U.S. patents related to three-dimensional semiconductor device structures and manufacturing methods.
  • Technical Context: The technology concerns monolithic three-dimensional integrated circuits (3D ICs), a method for vertically stacking and interconnecting layers of transistors to increase the density and performance of semiconductor devices beyond the limits of traditional two-dimensional scaling.
  • Key Procedural History: The complaint does not reference any prior litigation between the parties, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
2011-06-28 Earliest Priority Date for all Patents-in-Suit
2019-08-20 U.S. Patent No. 10,388,568 Issued
2022-10-18 U.S. Patent No. 11,476,181 Issued
2022-12-20 U.S. Patent No. 11,532,599 Issued
2023-02-07 U.S. Patent No. 11,575,038 Issued
2023-03-21 U.S. Patent No. 11,610,802 Issued
2023-10-17 U.S. Patent No. 11,791,222 Issued
2023-10-31 U.S. Patent No. 11,804,396 Issued
2024-01-02 U.S. Patent No. 11,862,503 Issued
2025-11-26 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,476,181 - "3D Semiconductor Device and Structure with Metal Layers"

  • Patent Identification: U.S. Patent No. 11,476,181, "3D Semiconductor Device and Structure with Metal Layers," issued October 18, 2022 (the "’181 Patent") (Compl. ¶27).

The Invention Explained

  • Problem Addressed: The patent family addresses the physical limitations of scaling transistors in two dimensions, which leads to diminishing returns in performance and density and increases the challenges associated with wire delay ('568 Patent, col. 1:38-44).
  • The Patented Solution: The invention proposes a monolithic 3D integrated circuit where subsequent layers of single-crystal silicon transistors are fabricated directly on top of lower layers of circuitry (Compl. ¶36; '181 Patent, Abstract). This monolithic approach allows for extremely dense, short vertical interconnections (vias) between transistor levels, in contrast to techniques that bond separately manufactured chips together with larger through-silicon vias ('568 Patent, col. 1:52-62).
  • Technical Importance: This monolithic 3D integration method enables a higher density of transistors and shorter interconnect paths than was achievable with prior 3D stacking technologies, potentially mitigating the "interconnect bottleneck" that limits performance in advanced semiconductor devices (Compl. ¶36-37).

Key Claims at a Glance

  • The complaint asserts at least claim 4 (Compl. ¶44). Claim 4 depends from independent claim 1.
  • The essential elements of independent claim 1, as modified by dependent claim 4, include:
    • A 3D semiconductor device comprising a first level with single crystal silicon transistors.
    • First, second, and third metal layers overlaying the first level.
    • A second level overlaying the first level, comprising a plurality of second transistors.
    • A fourth metal layer overlaying the second level.
    • A connective path (via) between the fourth metal layer and the second or third metal layers, with the via having a diameter between 5 nm and 500 nm.
    • At least one of the second transistors is vertically oriented.
    • The third metal layer is connected to provide a power or ground signal to at least one of the second transistors.
  • The complaint alleges infringement of "one or more claims" of the ’181 Patent (Compl. ¶43).

U.S. Patent No. 11,610,802 - "Method For Producing A 3D Semiconductor Device and Structure with Single Crystal Transistors and Metal Gate Electrodes"

  • Patent Identification: U.S. Patent No. 11,610,802, "Method For Producing A 3D Semiconductor Device and Structure with Single Crystal Transistors and Metal Gate Electrodes," issued March 21, 2023 (the "’802 Patent") (Compl. ¶28).

The Invention Explained

  • Problem Addressed: The patent addresses the need for an efficient manufacturing method for building complex, multi-layered 3D semiconductor devices ('802 Patent, col. 1:47-56).
  • The Patented Solution: The invention is a method for fabricating a 3D device. The process involves providing a first level with peripheral circuitry, forming multiple metal layers, and then sequentially forming at least two additional device levels ("second level" and "third level") on top. A key step is the simultaneous deposition of gate electrodes for transistors on both the second and third levels, which suggests a manufacturing efficiency ('802 Patent, Abstract; col. 2:54-67).
  • Technical Importance: The claimed method provides a pathway to construct multiple layers of memory cells monolithically, potentially streamlining the fabrication process for high-density 3D memory chips ('802 Patent, col. 1:57-61).

Key Claims at a Glance

  • The complaint asserts at least claim 8 (Compl. ¶63).
  • The essential steps of independent claim 8 include:
    • Providing a first level comprising a first single crystal layer and forming peripheral circuitry thereon.
    • Forming a first and second metal layer on top of the first level.
    • Forming at least one second level on top of the second metal layer and performing a first lithography step on it.
    • Forming at least one third level on top of the second level and performing a second lithography step on it.
    • Performing additional processing (deposition and etch) to form memory cells in the second and third levels.
    • Performing a deposition step to simultaneously deposit gate electrodes on transistors in both the second and third levels.
  • The complaint asserts infringement of "one or more claims" of the ’802 Patent (Compl. ¶62).

U.S. Patent No. 11,804,396 - "Methods for Producing A 3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers"

  • This method patent is similar to the ’802 Patent, describing a process for sequentially building multiple levels of memory cells. A key feature is the formation of "at least four independent memory arrays" from the fabricated memory cells (Compl. ¶81).
    • Patent Identification: U.S. Patent No. 11,804,396 ("'396 Patent"), issued October 31, 2023 (Compl. ¶29).
    • Asserted Claims: At least claim 1 (Compl. ¶81).
    • Accused Features: The manufacturing process of the Accused Products, which allegedly results in a die containing at least four independent NAND flash memory arrays (Compl. ¶91).

U.S. Patent No. 11,862,503 - "Method for Producing a 3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers"

  • This method patent is also similar to the ’802 Patent. It claims a process of forming two stacked levels of memory cells ("second" and "third" levels) and then simultaneously depositing gate electrodes for transistors in both levels (Compl. ¶100).
    • Patent Identification: U.S. Patent No. 11,862,503 ("'503 Patent"), issued January 2, 2024 (Compl. ¶30).
    • Asserted Claims: At least claim 1 (Compl. ¶100).
    • Accused Features: The manufacturing process for the Accused Products, which allegedly includes forming two "decks" of NAND memory and simultaneously depositing their gate electrodes (Compl. ¶104, ¶107).

U.S. Patent No. 10,388,568 - "3D Semiconductor Device and System"

  • This patent claims a 3D device structure comprising a base layer of transistors forming peripheral circuits, with multiple memory cells stacked on top. The claims require that a third metal layer is "significantly thicker" than the first or second metal layers (Compl. ¶116).
    • Patent Identification: U.S. Patent No. 10,388,568 ("'568 Patent"), issued August 20, 2019 (Compl. ¶31).
    • Asserted Claims: At least claim 7 (Compl. ¶116).
    • Accused Features: The physical structure of the Accused Products, which allegedly includes memory peripheral circuits under a NAND memory array and has a third metal layer that is thicker than lower metal layers (Compl. ¶117-118, ¶122).

U.S. Patent No. 11,532,599 - "3D Semiconductor Device and Structure with Metal Layers"

  • This device patent claims a structure with five distinct metal layers. Key features include a second level of transistors, a connection path (via) through that second level, and a fifth metal layer that comprises a "global power distribution grid" and is at least 50% thicker than the second metal layer (Compl. ¶133).
    • Patent Identification: U.S. Patent No. 11,532,599 ("'599 Patent"), issued December 20, 2022 (Compl. ¶32).
    • Asserted Claims: At least claim 1 (Compl. ¶133).
    • Accused Features: The physical structure of the Accused Products, which allegedly contains five metal layers where the top metal layer is used for global power distribution and is significantly thicker than a lower metal layer (Compl. ¶135, ¶137, ¶140, ¶141).

U.S. Patent No. 11,575,038 - "3D Semiconductor Device and Structure With Memory"

  • This patent claims a 3D device with multiple levels of transistors and memory cells. A distinguishing feature is that memory cells in an upper level are "at least partially atop of said control circuits" in a lower level, and a fourth metal layer has a thickness "at least twice" that of a second metal layer (Compl. ¶152).
    • Patent Identification: U.S. Patent No. 11,575,038 ("'038 Patent"), issued February 7, 2023 (Compl. ¶33).
    • Asserted Claims: At least claim 1 (Compl. ¶152).
    • Accused Features: The "CMOS under Array" architecture of the Accused Products, where memory cells are stacked atop control circuits, and which allegedly have a fourth metal layer that is at least twice as thick as a lower metal layer (Compl. ¶158, ¶161).

U.S. Patent No. 11,791,222 - "3D Semiconductor Device and Structure"

  • This patent claims a 3D device with five metal layers and a via through the second transistor level. A key limitation is that the "typical thickness of said fifth metal layer is greater than a typical thickness of said fourth metal layer by at least 50%" (Compl. ¶172).
    • Patent Identification: U.S. Patent No. 11,791,222 ("'222 Patent"), issued October 17, 2023 (Compl. ¶34).
    • Asserted Claims: At least claim 8 (Compl. ¶172).
    • Accused Features: The physical structure of the Accused Products, which allegedly have five metal layers where the fifth is at least 50% thicker than the fourth (Compl. ¶173-174, ¶176).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the "Accused Products" as all of Defendant's 3D NAND memory products, including but not limited to various SSD series (PEB000, PS1000, etc.), NAND storage products (UE400, UD310, etc.), and eMMC products (Compl. ¶39). The SK hynix Platinum P51 SSD is used as a primary, representative example throughout the infringement analysis (Compl. ¶43).

Functionality and Market Context

  • The Accused Products are high-density semiconductor memory devices, such as Solid-State Drives (SSDs), that utilize a 3D NAND architecture (Compl. ¶39). The complaint alleges these devices employ a "CMOS under Array" (CUA) design, where the logic circuitry for controlling the memory is placed underneath the vertically stacked memory array (Compl. p. 14, image label). This CUA architecture is a known industry approach for increasing storage density. The complaint alleges that these products are critical components in modern electronics and are sold to major technology companies such as Dell, Nvidia, and AMD for use in servers, computers, and graphics cards (Compl. ¶14, ¶17-20). The complaint includes a screenshot from Dell's website listing various SK hynix drives used in Dell's servers (Compl. p. 6). NAND flash memory and DRAM products are alleged to constitute 29% and 63%, respectively, of Defendant's sales (Compl. ¶11).

IV. Analysis of Infringement Allegations

’181 Patent Infringement Allegations

Claim Element (from Independent Claim 1 as modified by Dependent Claim 4) Alleged Infringing Functionality Complaint Citation Patent Citation
a first level comprising a single crystal silicon layer and a plurality of first transistors, said plurality of first transistors each comprising a single crystal channel; The device's peripheral circuitry ("CMOS under Array") is formed on a single crystal silicon substrate, comprising a plurality of first transistors. ¶45 '568 Patent, col. 2:58-61
a first metal layer overlaying said plurality of first transistors; a second metal layer overlaying said first metal layer; a third metal layer overlaying said second metal layer; The device has multiple metal layers stacked above the CMOS circuitry, identified in SEM images as "a first metal layer," "a second metal layer," and "a third metal layer." ¶46 '181 Patent, col. 3:20-24
a second level, wherein said second level overlays said first level, wherein said second level comprises a plurality of second transistors; The 3D NAND array, comprising multiple decks of memory cells, constitutes the second level and contains a plurality of second transistors. ¶47 '181 Patent, col. 3:25-28
a fourth metal layer overlaying said second level; A fourth metal layer is present above the 3D NAND decks. ¶48 '181 Patent, col. 3:29-30
a connective path...comprises a via disposed through said second level, wherein said via has a diameter of less than 500 nm and greater than 5 nm, The device contains a connective path with a via passing through the 3D NAND array (second level), with a diameter alleged to be nominally 300 nm. ¶49-51 '181 Patent, col. 3:31-38
wherein at least one of said plurality of second transistors is vertically oriented, The transistors within the 3D NAND array are vertically oriented, with the channel oriented perpendicular to the substrate. The complaint provides a schematic and SEM cross-section illustrating this vertical orientation (Compl. p. 21). ¶52 '181 Patent, col. 3:39-41
and wherein said third metal layer is connected to provide a power or a ground signal to at least one of said plurality of second transistors. The bitline, which constitutes the third metal layer, is connected to provide voltage to the 3D NAND array. The complaint contains an SEM image purporting to show this connection (Compl. p. 22). ¶53 '181 Patent, col. 3:42-45
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the term "second level...compris[ing] a plurality of second transistors" as used in the patent can be construed to read on a dense 3D NAND memory array. A defendant could argue that the patent's specification describes the "second level" as containing logic-style transistors similar to the first level, rather than the specialized, vertically-stacked memory cells of a NAND array.
    • Technical Questions: The allegation that the "third metal layer is connected to provide a power or a ground signal" will likely be contested. What evidence does the complaint provide that the "bitline" (allegedly the third metal layer) is specifically providing a power/ground signal as claimed, rather than a data signal, and whether these functions are mutually exclusive in the context of the claim?

’802 Patent Infringement Allegations

Claim Element (from Independent Claim 8) Alleged Infringing Functionality (Inferred from Product Structure) Complaint Citation Patent Citation
providing a first level, said first level comprising a first single crystal layer; forming peripheral circuitry in and/or on said first level, wherein said peripheral circuitry comprises first single crystal transistors; The Accused Products are made by a process that provides a first level of single crystal silicon, on which CMOS peripheral circuits are formed. The complaint presents an SEM image showing the "CMOS under Array (CUA)" on "a first level" (Compl. p. 27). ¶64-65 '802 Patent, col. 2:54-59
forming a first metal layer on top of said first level; forming a second metal layer on top of said first metal layer; The manufacturing process forms first and second metal layers on top of the peripheral circuitry level. ¶66 '802 Patent, col. 2:60-61
forming at least one second level disposed on top of or above said second metal layer; performing a first lithography step on said second level; The process forms a first memory deck ("3D NAND deck 1") as the second level, which is formed by a lithography step. ¶66-67 '802 Patent, col. 2:62-64
forming at least one third level disposed on top of or above said at least one second level; performing a second lithography step on said third level; The process forms a second memory deck ("3D NAND deck 2") as the third level, which is also formed by a lithography step. ¶68 '802 Patent, col. 2:65-67
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level... The process includes deposition and etch steps (e.g., lithography, etching of memory tubes, dielectric depositions) to form the memory cells in each NAND deck. ¶69 '802 Patent, col. 3:1-9
and then performing a deposition step to simultaneously deposit gate electrodes on both said at least one second transistor and said at least one third transistor. The process allegedly forms a slit through both NAND decks, removes sacrificial material, and then simultaneously deposits the tungsten (W) gate electrodes for both decks. The complaint includes a diagram illustrating this alleged simultaneous deposition process (Compl. p. 35). ¶72 '802 Patent, col. 3:13-16
  • Identified Points of Contention:
    • Evidentiary Questions: The infringement allegation for this method patent is made under 35 U.S.C. § 271(g), which covers products made by a patented process. A primary dispute will be evidentiary: how will the plaintiff prove the actual manufacturing steps used by SK hynix in its confidential fabrication process? The complaint infers the process from analyzing the final product's structure, which a defendant will likely argue is insufficient to prove the specific sequence and nature of the claimed steps.
    • Technical Questions: The allegation of "simultaneously deposit[ing] gate electrodes" for transistors on two different levels (decks) will be a critical technical and factual dispute. The question will be whether SK hynix’s process actually performs this step, and what evidence beyond inference from the final structure supports this allegation.

V. Key Claim Terms for Construction

For the ’181 Patent:

  • The Term: "vertically oriented" [transistor]
  • Context and Importance: This term is central to distinguishing the claimed 3D structure from simple planar stacking. Plaintiff alleges the channel of the NAND memory cells is vertical (Compl. ¶52). Practitioners may focus on whether this term, in the context of the patent, requires a specific transistor architecture or merely an orientation where current flows perpendicular to the main substrate plane.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term is not explicitly defined in the ’181 patent itself. A party might argue that its plain and ordinary meaning simply requires the primary current path to be substantially perpendicular to the plane of the first level, which would cover the accused 3D NAND structure.
    • Evidence for a Narrower Interpretation: The specification of the parent '568 patent, from which the '181 patent is continued, may provide embodiments or descriptions of "vertically oriented" transistors that are structurally different from the gate-all-around charge trap transistors used in 3D NAND. For example, if the specification only shows vertical FinFETs or other specific structures, a defendant may argue the term is implicitly limited to those embodiments.

For the ’802 Patent:

  • The Term: "simultaneously deposit"
  • Context and Importance: This term defines the key manufacturing efficiency step. The infringement theory depends on proving that SK hynix deposits the gate electrodes for transistors on "deck 1" (the second level) and "deck 2" (the third level) in a single, simultaneous process step (Compl. ¶72). The construction of this term will determine the evidence required to prove infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party could argue that "simultaneously" should be construed practically to mean occurring within the same overall deposition tool and process cycle, even if not at the exact same moment in time, covering a process where a single deposition fills voids for gates on multiple levels. The specification describes a process to "simultaneously deposit gate electrodes for both second and third transistors" ('802 Patent, Abstract).
    • Evidence for a Narrower Interpretation: A defendant may argue that the term requires the material for the gate electrodes on the second and third levels to be deposited literally at the same time onto both levels from a common source in a single action. The patent figures illustrating the process, such as those showing the formation of gate electrodes after etching slits (e.g., '802 Patent, Fig. 37F), may be cited to argue for a specific physical process that the term is intended to cover.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. Inducement is alleged based on Defendant’s acts of "manufacturing, selling, distributing, and/or otherwise making available the Accused Products, and providing instructions, documentation, and other information to customers and end-users" that suggest infringing use (e.g., Compl. ¶55, ¶124). Contributory infringement is alleged on the basis that the accused components are material to the inventions, are not staple articles of commerce, and are known to be especially adapted for infringement (e.g., Compl. ¶56, ¶125).
  • Willful Infringement: Willfulness is alleged for all asserted patents. The complaint bases this on "information and belief" that SK hynix has "known of MonolithIC 3D's patents" and has either actual knowledge or has taken deliberate steps to avoid learning of the infringement (e.g., Compl. ¶57, ¶75). The allegations suggest pre-suit knowledge, though knowledge is also established "at least as of the filing of this Complaint" (Compl. ¶40).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of structural correspondence: Do the terms "level" and "transistor" as defined and described in the patents, which originate from a context of stacking logic layers, encompass the highly specialized, vertically stacked "decks" of charge-trap memory cells that constitute a modern 3D NAND array? The outcome may depend on whether the court views the claims as broadly covering any monolithic 3D stacking or as being limited to the specific transistor architectures described in the specification.
  • A key evidentiary question will be one of proving the manufacturing process: For the asserted method patents, the case will likely turn on whether Plaintiff can obtain and present sufficient evidence to prove that SK hynix's confidential fabrication process performs the exact sequence of steps claimed. The allegation of "simultaneously deposit[ing] gate electrodes" across two distinct vertical levels will be a central and technically complex factual dispute, likely requiring extensive discovery into Defendant's manufacturing operations.