DCT
2:25-cv-01183
Topwire LLC v. Samsung Electronics Co Ltd
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: TopWire LLC (Texas)
- Defendant: Samsung Electronics Co., Ltd. (Korea); Samsung Electronics America, Inc. (New York)
- Plaintiff’s Counsel: The McCarty Firm, P.C.
- Case Identification: 2:25-cv-01183, E.D. Tex., 12/01/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant Samsung Electronics America, Inc. maintains a regular and established place of business in the district, and Defendant Samsung Electronics Co., Ltd. is a foreign corporation subject to personal jurisdiction in the district.
- Core Dispute: Plaintiff alleges that Defendant’s double-layered logic boards, used in numerous Samsung smartphone models since 2019, infringe a patent related to semiconductor packaging structures that enable 3D stacking of substrates and chips.
- Technical Context: The technology concerns advanced semiconductor packaging, a critical field for increasing the component density and functionality of modern electronics, particularly in space-constrained devices like smartphones.
- Key Procedural History: The complaint alleges that Samsung had actual knowledge of the patent-in-suit as early as March 2022, when the patent was cited by a USPTO examiner during the prosecution of a Samsung patent application. Plaintiff also alleges it sent a notice letter to Samsung in September 2025, prior to filing the lawsuit.
Case Timeline
| Date | Event |
|---|---|
| 2015-06-24 | U.S. Patent No. 9,859,202 Priority Date |
| 2018-01-02 | U.S. Patent No. 9,859,202 Issued |
| 2019-08-23 | Accused Samsung Galaxy Note 10 / 10+ Launched |
| 2022-03-15 | Alleged date of Samsung's knowledge of '202 Patent via its patent prosecution |
| 2025-04-27 | '202 Patent assigned to Plaintiff TopWire LLC |
| 2025-09-19 | Plaintiff sent notice letter to Samsung |
| 2025-10-14 | Samsung responded to Plaintiff's notice letter |
| 2025-12-01 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,859,202 - "Spacer Connector"
- Patent Identification: U.S. Patent No. 9,859,202, "Spacer Connector," issued January 2, 2018 (’202 Patent).
The Invention Explained
- Problem Addressed: The patent background describes a problem in fabricating micro-scale circuitry where traditional methods require stripping a "seed layer" after plating, which can unintentionally reduce the size of the circuits, a critical issue in nanotechnology applications (ʼ202 Patent, col. 1:15-24).
- The Patented Solution: The patent discloses a physical structure—a "spacer connector"—designed to vertically connect two separate semiconductor package substrates while maintaining a defined space between them (ʼ202 Patent, col. 3:35-43). This spacer contains metal pillars that pass through a core substrate, enabling electrical communication between the top and bottom package substrates, which can hold different integrated circuits (ʼ202 Patent, Fig. 8; col. 2:36-42). This configuration facilitates a stacked, three-dimensional architecture for electronic components.
- Technical Importance: This type of vertical integration allows for a higher density of electronic components to be packaged within a smaller physical footprint, a key objective in the design of mobile and other compact electronic devices (Compl. ¶19).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶34).
- The essential elements of claim 1 include:
- A structure with a bottom and a top package substrate.
- At least one "spacer connector" positioned between the substrates to define a space.
- The spacer connector itself comprises a core substrate, metal pillars passing through it, and top metal pads on the pillars.
- A specific structural requirement that the bottom end of each metal pillar "protrudes downwardly" from the core substrate's bottom surface.
- Electrical coupling between the top and bottom substrates through the spacer connector's pillars.
- A bottom chip arranged in the space between the substrates and mounted on the bottom substrate.
- A specific arrangement where the structure uses "two spacer connectors arranged on opposite sides of the bottom chip."
- The complaint reserves the right to assert additional claims (Compl. ¶32, fn. 7).
III. The Accused Instrumentality
Product Identification
The accused products are Samsung smartphones released since the Galaxy Note 10 and Galaxy Note 10+ that include a "double-layered logic board" (Compl. ¶23, 25). The Samsung Galaxy S23 Ultra is used as a representative example for infringement analysis (Compl. ¶35).
Functionality and Market Context
The complaint alleges that beginning with the Galaxy Note 10 in 2019, Samsung adopted a new logic board design featuring two substrates stacked together (Compl. ¶23). This design allegedly allows Samsung to support more integrated circuits and functionality without increasing the board's surface area, providing a competitive advantage by enabling "maximum space savings" (Compl. ¶23, fn. 5; ¶31). The complaint provides a photograph of the logic board from a Samsung Galaxy Note 10 to illustrate this double-layered structure (Compl. p. 7).
IV. Analysis of Infringement Allegations
U.S. Patent No. 9,859,202 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A structure, comprising: a bottom package substrate; a top package substrate stacked on top of the bottom package substrate; | The logic board in the accused Samsung Galaxy S23 Ultra is alleged to be a structure containing a bottom package substrate and a top package substrate stacked upon it. | ¶40-42 | col. 3:31-34 |
| at least one spacer connector interposed between the bottom package substrate and the top package substrate to define a space between the bottom package substrate and the top package substrate... | The logic board allegedly includes at least one spacer connector between the two substrates, creating a defined space. A cross-sectional image with annotations highlights this alleged structure (Compl. p. 14). | ¶43 | col. 3:35-39 |
| wherein the spacer connector comprises a core substrate; a plurality of metal pillars, each passing through the core substrate; and a plurality of top metal pads, each on a top end of a corresponding metal pillar... | Scanning electron microscope (SEM) images of the accused logic board's connector are provided, with annotations identifying the alleged core substrate, metal pillars, and top metal pads (Compl. p. 15). | ¶44 | col. 3:40-45 |
| wherein a bottom end of each metal pillar among the plurality of metal pillars protrudes downwardly from a bottom surface of the core substrate, | The complaint alleges this feature is present and provides SEM images that purport to show the bottom end of the metal pillars (Compl. p. 15-16). | ¶44 | col. 3:46-49 |
| the top package substrate is electrically coupled to the bottom package substrate through the plurality of bottom metal pillars of the top package substrate, the plurality of metal pillars of the spacer connector, and the plurality of top metal pillars of the bottom package substrate; | Plaintiff alleges that electrical signals flow between the two substrates via the various pillars of the spacer connector and substrates. | ¶47 | col. 3:56-62 |
| a bottom chip arranged in the space between the bottom package substrate and the top package substrate, wherein the bottom chip is mounted to the top surface of the bottom package substrate... | The complaint provides an annotated cross-sectional photograph allegedly showing a "Bottom Chip" located in the space between the two substrates and mounted on the bottom substrate (Compl. p. 18). | ¶48-49 | col. 3:63-col. 4:2 |
| and the at least one spacer connector comprises two spacer connectors arranged on opposite sides of the bottom chip. | A cross-sectional image is provided with annotations pointing to two distinct "Spacer Connectors" on opposite sides of the internal cavity where the bottom chip is located (Compl. p. 19). | ¶50 | col. 4:3-5 |
Identified Points of Contention
- Scope Questions: A central question may be whether the integrated interconnects within Samsung's multi-layered logic board constitute a "spacer connector" as that term is used in the patent. The defense may argue that the claimed "spacer connector" is a discrete component manufactured separately, whereas the accused structure is an inseparable part of the logic board assembly.
- Technical Questions: The analysis may focus on whether the accused structures meet the specific geometric and positional limitations of the claim. For instance, what evidence demonstrates that the bottom end of the metal pillars "protrudes downwardly" from the core substrate, rather than being flush or embedded? Further, does the accused product's architecture contain precisely "two spacer connectors arranged on opposite sides of the bottom chip," or is the structure different in a way that avoids this limitation?
V. Key Claim Terms for Construction
"spacer connector"
- Context and Importance: This term is the central inventive concept of the patent. The entire infringement case rests on whether the structures connecting the two layers of Samsung's logic board fall within the legal definition of a "spacer connector."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent repeatedly describes the term by its function: a structure "interposed between the bottom package substrate and the top package substrate to define a space" (ʼ202 Patent, col. 3:35-39). Plaintiff may argue that any structure performing this spacing and connecting function meets the definition.
- Evidence for a Narrower Interpretation: The specification provides detailed descriptions and figures of specific embodiments (e.g., ʼ202 Patent, Fig. 7B, 10B, 13B). A defendant could argue that the term should be limited to these disclosed structures, which appear to be discrete components, potentially distinguishing them from a fully integrated logic board interconnect.
"protrudes downwardly from a bottom surface of the core substrate"
- Context and Importance: This is a precise structural limitation that differentiates the claimed invention from other potential interconnect designs. If the accused pillars do not "protrude," there may be no literal infringement of this element. Practitioners may focus on this term because micro-scale manufacturing can create structures that are flush or embedded, and the distinction will rely on expert interpretation of microscopic evidence.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Plaintiff may argue that any extension of the pillar's bottom end beyond the plane of the core substrate's bottom surface, however small, satisfies the "protrudes" requirement.
- Evidence for a Narrower Interpretation: The patent figures, particularly Figure 10A, depict a distinct bottom end (155) extending below the core substrate (11) in a cantilever-like fashion before any further connection is made (ʼ202 Patent, col. 2:51-53). A defendant may argue this context requires a more substantial, unsupported extension than might be present in its integrated structure.
VI. Other Allegations
- Indirect Infringement: The complaint alleges Samsung induced infringement by third parties (e.g., customers, retailers) by "advertising, encouraging, instructing, providing support for, and/or operating the Accused Products" through materials like specifications, instruction manuals, and user guides (Compl. ¶53).
- Willful Infringement: Willfulness is alleged based on both pre-suit and post-filing conduct. The complaint asserts that Samsung had actual knowledge of the ’202 Patent since at least March 15, 2022, because the patent was cited by the USPTO examiner and subsequently cited by Samsung itself in an Information Disclosure Statement during the prosecution of Samsung's own patent application (Compl. ¶56). Further, the complaint alleges that a pre-suit notice letter sent on September 19, 2025, provided an independent basis for knowledge (Compl. ¶58).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "spacer connector," described in the patent as a component for connecting substrates, be construed to read on the integrated vertical interconnects within Samsung's multi-layered logic board, or is there a fundamental structural distinction between the two?
- A second issue will be one of evidentiary proof: does the microscopic physical evidence from the accused Samsung smartphones satisfy every precise structural limitation of Claim 1, such as the requirement that metal pillars "protrude downwardly" and that there are exactly "two" connectors arranged on "opposite sides" of a chip?
- A final key question will be one of culpability: given the complaint's allegation that Samsung was aware of the ’202 Patent for over three years before the suit was filed due to its own patent prosecution activities, the case may turn on whether Samsung's continued sale of the accused smartphones constitutes willful infringement, potentially exposing it to enhanced damages.