DCT

2:25-cv-01260

Neolayer LLC v. ASUSTeK Computer Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-01260, E.D. Tex., 12/31/2025
  • Venue Allegations: Venue is alleged to be proper because the defendant is a foreign corporation not resident in the United States and has committed acts of patent infringement within the district. The complaint also notes that the defendant and its subsidiaries have previously filed patent infringement lawsuits in the same district, thereby availing themselves of the court.
  • Core Dispute: Plaintiff alleges that Defendant’s consumer electronics products incorporating OLED displays infringe six patents related to semiconductor structure, fabrication methods, and display apparatus architecture.
  • Technical Context: The patents relate to the design and manufacturing of components for high-resolution displays, particularly the thin-film transistors (TFTs) and pixel structures used in OLED panels, a technology central to modern smartphones, monitors, and laptops.
  • Key Procedural History: The complaint alleges that the Defendant had actual knowledge of its infringement of the asserted patents no later than August 12, 2025, upon receiving a notice letter from the Plaintiff dated August 5, 2025. This allegation forms the basis for the claim of willful infringement.

Case Timeline

Date Event
2007-03-15 Priority Date for U.S. Patent No. 7,649,583
2008-07-25 Priority Date for U.S. Patent No. 8,093,592
2010-01-19 U.S. Patent No. 7,649,583 Issued
2010-10-29 Priority Date for U.S. Patent No. 8,330,358
2010-12-24 Priority Date for U.S. Patent No. 8,698,712
2011-12-22 Priority Date for U.S. Patent No. 8,674,365
2012-01-10 U.S. Patent No. 8,093,592 Issued
2012-12-11 U.S. Patent No. 8,330,358 Issued
2014-03-18 U.S. Patent No. 8,674,365 Issued
2014-04-15 U.S. Patent No. 8,698,712 Issued
2019-01-01 Approximate Launch of Accused ASUS OLED Products in U.S.
2019-03-28 Priority Date for U.S. Patent No. 11,088,129
2021-08-10 U.S. Patent No. 11,088,129 Issued
2025-07-01 Asserted Patents Assigned to NeoLayer LLC
2025-08-12 ASUS Allegedly Received Notice of Infringement
2025-12-31 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,649,583 - *"Semiconductor Structure and Fabricating Method Thereof for Liquid Crystal Display Device"*

The Invention Explained

  • Problem Addressed: The patent's background describes that conventional methods for fabricating pixel structures with storage capacitors in displays like LCDs require numerous expensive photomasks, increasing production costs, and can result in poor display quality due to insufficient storage capacitance (’583 Patent, col. 1:49-col. 2:33).
  • The Patented Solution: The invention claims a specific multi-step method for fabricating a semiconductor structure that integrates a multi-layer storage capacitor. This method involves sequentially forming and patterning multiple inter-layer dielectric and conductive layers to create both the active transistor elements and a high-capacitance storage structure, allegedly with a reduced number of photomasks (’583 Patent, col. 2:34-51; Abstract). The structure involves creating a capacitor from three stacked layers: a semiconductor layer, a first electrode, and a second electrode, separated by dielectrics (’583 Patent, col. 9:11-30).
  • Technical Importance: This method purports to increase storage capacitance, which improves display quality, while potentially lowering manufacturing costs by simplifying the fabrication process (’583 Patent, col. 2:34-42).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (’583 Patent, col. 13:6-col. 14:4; Compl. ¶36).
  • Claim 1 recites a method for fabricating a semiconductor structure, with essential steps including:
    • forming a semiconductor layer on a substrate in both an active element area and a storage capacitor area
    • forming a first inter-layer dielectric layer
    • forming a gate (in the active area) and a first electrode (in the capacitor area)
    • performing a doping process to form a source and drain
    • forming a second inter-layer dielectric layer over the gate and first electrode
    • forming a patterned conductive layer as a pixel electrode
    • forming a third inter-layer dielectric layer
    • patterning the dielectric layers to form contact windows
    • forming a second electrode and a source/drain conductive line
  • The complaint does not explicitly reserve the right to assert dependent claims but notes that its selection of claims is not limiting (Compl. ¶33).

U.S. Patent No. 8,093,592 - *"Thin Film Transistor Substrate, Electronic Apparatus, and Methods For Fabricating The Same"*

The Invention Explained

  • Problem Addressed: The patent background explains that in polysilicon thin-film transistors (TFTs), electrical performance is highly dependent on the orientation of crystalline "sub-grain boundaries" (SGBs). Carrier mobility is reduced when charge flows parallel to main grain boundaries (MGBs), and conventional rectangular TFT layouts can lead to inconsistent performance depending on their orientation on the substrate, causing display non-uniformity (mura effects) (’592 Patent, col. 2:11-47).
  • The Patented Solution: The invention proposes a TFT structure where the channel region—the path between the source and drain—is "extended along a curve." This curved path ensures that carriers must cross a plurality of SGBs, regardless of the TFT's overall orientation, thereby averaging out the anisotropic effects and leading to more uniform electrical properties across the display (’592 Patent, col. 3:11-20; Abstract). Figure 7A illustrates a channel region (230C) following a curved path (C2L) between the source (230S) and drain (230D) (’592 Patent, col. 8:1-12).
  • Technical Importance: This design aims to improve the uniformity of electrical characteristics for TFTs across a display substrate, which is critical for reducing visual defects and improving overall display quality (’592 Patent, col. 2:42-47).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (’592 Patent, col. 11:51-col. 12:12; Compl. ¶57).
  • Claim 1 recites a thin film transistor substrate with essential elements including:
    • a substrate
    • at least a thin film transistor disposed on the substrate, comprising:
      • a semiconductor island with a plurality of sub-grain boundaries, a source region, a drain region, and a channel region
      • wherein a length of the channel region projected in the substrate is extended along a curve
      • and the width of the channel region projected in the substrate remains substantially the same in an extending direction of the curve
      • a gate, corresponding to the channel region
  • The complaint does not explicitly reserve the right to assert dependent claims but notes that its selection of claims is not limiting (Compl. ¶33).

U.S. Patent No. 8,698,712 - *"Pixel Structure of Active Matrix Organic Electroluminescent Display Panel and Method of Making the Same"*

  • Technology Synopsis: The patent describes a pixel structure for an OLED display panel that includes two separate light-emitting devices and their associated driving circuits within a single pixel region (’712 Patent, Abstract). This architecture is intended to enable a display to switch between a single-sided and double-sided display mode (’712 Patent, col. 1:40-45).
  • Asserted Claims: Independent claim 10 (Compl. ¶70).
  • Accused Features: The complaint alleges that the pixel structure of the ASUS Notebook PC Q423S, which contains a "first light emitting device" and a "second light emitting device" along with their respective driving and addressing switching devices, infringes the ’712 Patent (Compl. ¶71-76).

U.S. Patent No. 8,330,358 - *"OLED Illumination Device with Improved Aperture Ratio"*

  • Technology Synopsis: The patent addresses the problem of opaque metal signal lines reducing the light-emitting area ("aperture ratio") in OLED devices (’358 Patent, col. 1:26-44). The proposed solution involves a specific layered structure where a "first metal line" (signal line) is designed to overlap in vertical projection with a "second metal line" that is part of the pixel's sub-emitting area, thereby minimizing the area lost to signal routing (’358 Patent, Abstract).
  • Asserted Claims: Independent claim 1 (Compl. ¶82).
  • Accused Features: The complaint accuses the illumination device in the ASUS ROG Phone 9, alleging it has a transparent substrate with emitting and peripheral areas, and a structure where "first metal lines" are routed such that they overlap with "second metal lines" in different sub-emitting areas (Compl. ¶84-91). A top-down view with layers removed shows a "first metal line" passing through multiple sub-emitting areas (Compl. ¶91).

U.S. Patent No. 8,674,365 - *"Array Substrate and Manufacturing Method Thereof"*

  • Technology Synopsis: The patent describes an array substrate structure and a simplified manufacturing method for creating it (’365 Patent, Abstract). The structure includes a specific stack of layers for a thin film transistor, including a gate electrode, patterned insulating and semiconductor layers, a patterned etching stop layer, and a protective layer with contact openings to connect to the source/drain electrodes (’365 Patent, col. 2:10-40).
  • Asserted Claims: Independent claim 1 (Compl. ¶97).
  • Accused Features: The complaint alleges the ASUS ROG Phone 9 includes the claimed array substrate, pointing to its layered TFT structure comprising a gate electrode on the substrate, followed by patterned insulating, semiconductor, and etching stop layers, and a protective layer with contact openings for the source and drain electrodes (Compl. ¶98-107).

U.S. Patent No. 11,088,129 - *"Display Apparatus"*

  • Technology Synopsis: The patent discloses a display apparatus with a stacked structure involving two circuit layers separated by an adhesive layer (’129 Patent, Abstract). A key feature is the electrical connection between the two circuit layers, which is achieved via a "first via" that passes through both the adhesive layer and an insulating sublayer within the second circuit layer's thin-film transistor (’129 Patent, Abstract; col. 2:57-65).
  • Asserted Claims: Independent claim 1 (Compl. ¶113).
  • Accused Features: The complaint alleges the ASUS ROG Phone 9 embodies this display apparatus, identifying a first and second circuit layer separated by an adhesive layer (Compl. ¶116-118). It alleges a "first conductive element" connects the two circuit layers through a "first via" in the adhesive layer and a via in the insulating sublayer of a TFT (Compl. ¶119, ¶122).

III. The Accused Instrumentality

Product Identification

  • The complaint names specific products: the ASUS ROG Phone 9 AI2501B ("Accused Phone") and the ASUS Notebook PC Q423S ("Accused Computer") (Compl. ¶36, ¶70). It also broadly accuses a category of "Accused Products," including ASUS monitors, laptops, tablets, smartphones, and portable screens that incorporate OLED displays (Compl. ¶30).

Functionality and Market Context

  • The accused products are consumer electronics that utilize active-matrix OLED (AMOLED) displays (Compl. ¶37, ¶71, ¶83, ¶114). The complaint alleges that these displays are a core component and a key marketing feature, providing benefits like high contrast and fast response times (Compl. ¶22, ¶27). The complaint alleges ASUS has gained significant market share in the OLED monitor market, surpassing competitors (Compl. ¶26). The complaint provides a screenshot of marketing materials for the ROG Phone 9, which highlights its "cutting-edge 6.78" E6 AMOLED display" (Compl. ¶37). It also provides a photo of the ASUS Notebook PC Q423S, identifying its "active matrix organic electroluminescent display panel" (Compl. ¶71).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,649,583 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for fabricating a semiconductor structure, comprising: forming a semiconductor layer on a substrate... The manufacturing process for the Accused Phone's AMOLED display involves fabricating a semiconductor structure. A scanning electron microscope (SEM) image shows a "semiconductor layer" on a "substrate" in both an "active element area" and "storage capacitor area." ¶37-38 col. 7:16-20
forming a first inter-layer dielectric layer to cover the semiconductor layer; The process includes forming a first inter-layer dielectric layer covering the semiconductor layer, as depicted in an SEM cross-section. ¶39 col. 7:42-43
forming a gate on the first inter-layer dielectric layer in the active element area and a first electrode on the first inter-layer dielectric layer in a storage capacitor area; A gate is formed in the active element area and a first electrode is formed in the storage capacitor area, both on the first inter-layer dielectric layer. ¶40 col. 7:44-55
performing a doping process to form a source and a drain in the semiconductor layer in the active element area... A doping process is performed to create a source and drain. A top-down microscope view shows the source, drain, and channel within the active element area. ¶41 col. 8:1-5
forming a second inter-layer dielectric layer to cover the gate and the first electrode; A second inter-layer dielectric layer is formed over the gate and first electrode, as shown in an SEM image. ¶42 col. 8:6-8
forming a patterned conductive layer on the second inter-layer dielectric layer as a pixel electrode; A patterned conductive layer, serving as a pixel electrode, is formed on the second inter-layer dielectric layer. ¶43 col. 8:9-12
forming a third inter-layer dielectric layer to cover the patterned conductive layer; A third inter-layer dielectric layer is formed to cover the patterned conductive layer. ¶44 col. 8:13-14
patterning the third inter-layer dielectric layer to expose the patterned conductive layer and forming a plurality of contact windows in the first, second and third inter-layer dielectric layers... The third dielectric layer is patterned to expose the conductive layer, and contact windows are formed through the dielectric layers. ¶45-46 col. 8:15-23
forming a second electrode on the third inter-layer dielectric layer... and a source/drain conductive line electrically connecting the semiconductor layer with the patterned conductive layer. A second electrode is formed over and connected to the first electrode, and a source/drain conductive line is formed to connect the semiconductor layer to the patterned conductive layer. ¶48-49 col. 8:24-30
  • Identified Points of Contention:
    • Process Questions: The complaint asserts infringement of a method claim based on analysis of the final product structure. A central question will be whether the specific sequence of steps recited in claim 1 was actually used to manufacture the accused semiconductor structure, or if an alternative, non-infringing process was used that resulted in a similar final structure.
    • Scope Questions: The patent title and background focus on Liquid Crystal Display (LCD) devices (’583 Patent, Title; col. 2:48-51). A potential issue is whether the method claim, though not explicitly limited to LCDs, can be interpreted as applying to the fabrication of AMOLED displays, which operate on a different principle.

U.S. Patent No. 8,093,592 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A thin film transistor substrate, comprising: a substrate; The Accused Phone contains a thin-film transistor substrate that includes a substrate, as shown in an SEM cross-section. ¶58-59 col. 11:51-53
at least a thin film transistor, disposed on the substrate... The substrate has at least one thin film transistor disposed upon it. ¶60 col. 11:54-55
a semiconductor island, comprising a plurality of sub-grain boundaries... The transistor includes a semiconductor island which comprises multiple "sub grain boundaries," as identified in an SEM image. ¶61 col. 11:56-57
a source region, a drain region, and a channel region disposed between the source region and the drain region... The semiconductor island contains source, drain, and channel regions, as shown in a top-down microscope view with layers removed. ¶62 col. 11:57-59
wherein a length of the channel region projected in the substrate is extended along a curve... The length of the channel region follows a curved path, as illustrated in a top-down microscope view. ¶63 col. 11:59-62
and the width of the channel region projected in the substrate remains substantially the same in an extending direction of the curve; The width of this curved channel region is alleged to remain substantially the same along its length. The complaint's visual evidence indicates this with double-headed arrows (Compl. ¶63, Image). ¶63 col. 12:1-4
and a gate, corresponding to the channel region. A gate corresponding to the curved channel region is present, as shown in both top-down and cross-sectional views. ¶64 col. 12:5-6
  • Identified Points of Contention:
    • Definitional Scope: The interpretation of "extended along a curve" will be critical. The defendant may argue that the path shown in the complaint's evidence is not a "curve" within the patent's meaning but rather a series of linear segments or a minor deviation insufficient to meet the claim limitation.
    • Technical & Factual Questions: The limitation that the channel width "remains substantially the same" raises a factual question of degree. The parties may dispute the extent to which the width varies along the curved path in the accused device and whether that variation falls within the scope of "substantially the same." The complaint's use of microscope images suggests this will be a fact-intensive inquiry (Compl. ¶63).

V. Key Claim Terms for Construction

U.S. Patent No. 8,093,592

  • The Term: "extended along a curve"

  • Context and Importance: This term is the central novelty of claim 1, intended to distinguish the invention from prior art TFTs with linear or rectangular channels. The entire infringement theory for this patent rests on whether the accused transistor's channel region meets this geometric definition. Practitioners may focus on this term because its construction will determine whether the accused product's non-linear channel path infringes.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes various embodiments, including a channel region with a single inflection point (Fig. 7A, curve C2L) and another with two curved ends connected by a straight portion (Fig. 7B, curve C3). This suggests "curve" is not limited to a continuously curving line and could encompass paths with both curved and linear segments (’592 Patent, col. 8:1-24).
    • Evidence for a Narrower Interpretation: The patent’s objective is to ensure carriers cross a plurality of SGBs to average out anisotropic effects (’592 Patent, col. 3:11-20). A defendant may argue that "curve" must be construed to require a degree of curvature sufficient to achieve this technical purpose, potentially excluding minor or insignificant deviations from a straight line. The figures consistently show smooth, pronounced curves, which could be argued to limit the scope of the term.

  • The Term: "substantially the same"

  • Context and Importance: This term qualifies the width of the curved channel region. The infringement analysis will depend on how much variation in width is permissible. Practitioners may focus on this term because if the accused device's channel width varies beyond the construed scope of "substantially," the claim is not infringed.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The term "substantially" is a term of approximation, suggesting that minor variations in width due to manufacturing tolerances or design are permitted. The patent does not provide any numerical limits, which may support a construction that allows for a degree of variation that does not materially affect the transistor's function.
    • Evidence for a Narrower Interpretation: The specification states that keeping the width the same allows for uniform electrical properties (’592 Patent, col. 3:11-20). A defendant could argue that "substantially the same" must be interpreted functionally, meaning any width variation that leads to non-uniform electrical properties falls outside the claim scope. The drawings (e.g., Fig. 7B) depict a channel with a visually consistent width, which could be used to argue for a narrow range of permissible deviation.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for all asserted patents, stating that ASUS intentionally aids and encourages third parties (including vendors, customers, and partners) to use and sell the Accused Products with knowledge and specific intent that their acts constitute infringement (Compl. ¶52, ¶66, ¶78, ¶93, ¶109, ¶124).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for this allegation is ASUS's alleged actual knowledge of infringement since "no later than August 12, 2025, when ASUS received NeoLayer's August 5, 2025 letter" notifying it of the infringement (Compl. ¶54, ¶68, ¶80, ¶95, ¶111, ¶126).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of process versus product: For the '583 patent, can the plaintiff prove, based on reverse engineering the final product, that the defendant's suppliers used the specific multi-step method claimed, or will this present a significant evidentiary hurdle?
  • A key question of definitional scope will arise for the '592 patent: How much deviation from a straight line constitutes a "curve" under the patent's claims, and does the accused device's channel geometry meet that definition?
  • The case will likely involve a significant factual and technical dispute supported by competing expert analysis of physical evidence: Do the microscopic structures within the accused phones and laptops, as revealed by SEM and other imaging techniques, actually possess the specific layered configurations and geometric properties required by the asserted claims?