DCT

2:26-cv-00032

Mr Licensing LLC v. Renesas Electronics Corp

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00032, E.D. Tex., 01/13/2026
  • Venue Allegations: Venue is alleged as proper because the Defendant is a foreign corporation, which may be sued in any judicial district, and because Defendant allegedly places its products into the stream of commerce terminating in the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s RL78 line of microcontrollers infringes three patents related to semiconductor memory write-protection, low-power mode management, and watchdog timer functionality.
  • Technical Context: The technologies at issue relate to fundamental methods for managing power consumption, data security, and operational stability within microcontrollers, which are ubiquitous components in automotive, industrial, and consumer electronics.
  • Key Procedural History: The complaint alleges that the previous owner of the patents-in-suit, Monterey Research, LLC, had "extensive communications" with Defendant regarding its patent portfolio. It further alleges that Defendant took "affirmative steps to avoid learning of its infringement," forming the basis for the willfulness allegations.

Case Timeline

Date Event
2006-01-31 ’664 Patent Priority Date
2006-12-22 ’477 Patent Priority Date
2009-06-30 ’664 Patent Issue Date
2009-07-21 ’477 Patent Issue Date
2009-08-26 ’911 Patent Priority Date
2015-03-10 ’911 Patent Issue Date
2020-01-01 Accused Products first sold (approx. "since January of 2020")
2026-01-13 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,565,477, *“Semiconductor device and method of controlling the same,”* issued July 21, 2009 (’477 Patent)

The Invention Explained

  • Problem Addressed: The patent describes the need for a more efficient and flexible way to implement write-protection across multiple memory regions in a semiconductor device, particularly a method to disable programming in several regions at once without requiring a large and complex circuit area (’477 Patent, col. 2:41-51).
  • The Patented Solution: The invention proposes a hierarchical control system. Each memory region has its own setting to enable or disable programming (a "first program disabling information"). A separate, global setting (a "collective program disabling information") can override all the individual settings to disable programming across all regions simultaneously. A "selection circuit" processes these two inputs, enforcing the global override when active, but otherwise deferring to the individual region’s setting (’477 Patent, Abstract; Fig. 3).
  • Technical Importance: This approach allows for both granular, per-region write-protection and a global, high-priority security lockdown, providing enhanced flexibility for managing non-volatile memory.

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶20).
  • Claim 1 requires:
    • A plurality of memory regions with non-volatile memory cells.
    • A plurality of disabling information memory units, each storing "first program disabling information" indicating whether programming is enabled/disabled for its corresponding memory region.
    • A "program disabling information selection circuit" that outputs a "second program disabling information." This circuit outputs the "first program disabling information" when collective programming is not disabled, but outputs information to disable programming regardless of the first information when collective programming is disabled.
    • A program control circuit that disables or enables programming in the memory region based on the "second program disabling information" from the selection circuit.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,555,664, *“Independent control of core system blocks for power optimization,”* issued June 30, 2009 (’664 Patent)

The Invention Explained

  • Problem Addressed: The patent notes that conventional microcontrollers offer a limited set of pre-defined, non-customizable power modes that apply to the entire device, lacking the ability to independently manage the power consumption of specific internal "core system blocks" (’664 Patent, col. 1:13-21).
  • The Patented Solution: The invention describes a method where a power management unit can independently control and reduce power consumption of individual "core system blocks" (e.g., a voltage reference or power supply monitor) by "sampling" them. This involves periodically powering a block on just long enough to perform its function and then powering it off, a process that can occur even while the main processor is in a sleep state (’664 Patent, Abstract; col. 2:36-41).
  • Technical Importance: This technique enables fine-grained power management within a processing device, which can significantly reduce average power consumption, thereby extending battery life in portable electronics.

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶37).
  • Claim 1 requires a method comprising:
    • Providing power management commands to a power management unit of a processing device, where the unit is coupled to a core system block.
    • The power management commands are provided under control of a processor.
    • Sampling the core system block under control of the power management unit in response to the commands.
    • The sampling includes "periodically powering" the core system block while the processor is in a sleep mode.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,977,911, *“Watchdog timer with mode dependent time out,”* issued March 10, 2015 (’911 Patent)

Technology Synopsis

The patent addresses the issue of watchdog timers in systems with multiple power or performance modes. A fixed timeout period may be inappropriate for all modes, potentially causing false resets in low-power states or allowing errors to persist too long in high-speed states. The patented solution is a watchdog timer that receives an indication of a change in the system's mode of operation and, in response, changes its timeout value to one appropriate for the new mode (’911 Patent, Abstract; col. 1:40-51).

Asserted Claims

At least independent claim 1 (Compl. ¶49).

Accused Features

The complaint accuses the watchdog timer in the Renesas RL78/G23 microcontrollers. It alleges that when the microcontroller enters a HALT or STOP mode, the watchdog timer is set to stop counting, and upon exiting that mode, the timer's counter is reset to zero. This operational change is alleged to constitute changing the timer's timeout value in response to the change in mode (Compl. ¶¶50-52).

III. The Accused Instrumentality

Product Identification

All versions and variants of the Renesas RL78 microcontroller sold since January 2020 (Compl. ¶12).

Functionality and Market Context

  • The accused RL78 devices are described as energy-efficient, chip-based microcontrollers (Compl. ¶21). The complaint focuses on three specific functionalities:
    1. Memory Protection: The devices include a "FLASH Shield Window Function" and other security registers (e.g., BTPR bit) that allegedly allow for per-region programming control, and an FLPMC register that allegedly provides a collective override to disable programming for the entire code and data flash memory (Compl. ¶¶23-26).
    2. Power Management: The devices feature low-power modes, including a "SNOOZE" mode, where the main CPU clock is stopped but specific peripherals (A/D converter, UART, etc.) can be temporarily activated by a trigger to perform a function before the device returns to a low-power state, all without waking the CPU (Compl. ¶¶38, 40). A state diagram from a Renesas application note is provided as evidence of these modes (Compl. p. 23, Fig. 1).
    3. Watchdog Timer: The devices include a watchdog timer to detect malfunctions. The timer's operation can be configured to stop when the device enters HALT, STOP, or SNOOZE modes by setting the WDSTBYON bit, and to resume counting from a reset state upon exiting those modes (Compl. ¶¶50-52).
  • The complaint alleges the products are available for purchase directly from Defendant's website and are sold through intermediaries to customers such as Toyota (Compl. ¶¶4-5). A screenshot shows a product page for the RL78/G23 microcontroller (Compl. p. 3).

IV. Analysis of Infringement Allegations

’477 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of memory regions that include non-volatile memory cells The RL78 products include non-volatile code and data memory regions comprised of FLASH memory cells. ¶22 col. 3:12-14
a plurality of disabling information memory units that correspond to the memory regions, each...storing first program disabling information The products include a "FLASH Shield Window Function" via FSWS/FSWE registers, a BTPR bit for the boot area, and a DFLEN bit for data memory, which store information indicating whether programming is disabled for corresponding memory regions. ¶¶23-25 col. 3:15-20
a program disabling information selection circuit that outputs second program disabling information...regardless of the first program disabling information, when programming is disabled collectively...[and] outputting the first program disabling information...when programming is not collectively disabled The products include an FLPMC register with bits (FWEDIS, FLSPM) that enable/disable programming collectively for the code and data flash. When these bits are set to disable, programming is disabled regardless of the individual settings. When not set, the individual settings control programming. ¶¶26-28 col. 3:21-34
a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information The products inherently include a program control circuit that uses the output of the selection logic (based on the state of the FLPMC register and other settings) to disable or enable programming in the FLASH memory. ¶¶27-28 col. 3:35-39

Identified Points of Contention (’477 Patent)

  • Scope Questions: A central question may be whether the accused FLPMC register, which stores bits that are read and acted upon by the system, constitutes a "program disabling information selection circuit" as claimed. The claim language suggests a hardware circuit that actively selects between inputs, which may raise a dispute over whether a software-readable register meets this structural limitation.
  • Technical Questions: What evidence demonstrates that the accused device "inherently includes" the claimed selection and control circuits? The complaint asserts this inherency (Compl. ¶27), but the analysis may depend on the specific logic gates or microcode that interpret the various register bits to produce a final programming enable/disable signal. The complaint includes a table from the user manual showing the bits in the FLPMC register (Compl. p. 17, Fig. 33-14), which will be central to this analysis.

’664 Patent Infringement Allegations

| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|:---------------------------------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------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|
| providing power management commands to a power management unit of a processing device | Software application instructions for entering HALT, STOP, and SNOOZE modes are provided to the power management unit (clock generator, standby controller, etc.). | ¶39 | col. 2:42-44 |
| wherein the power management unit is coupled to a core system block of the processing device | The power management unit is coupled to and affects the operation of peripheral devices such as an A/D converter, simplified SPI ("CSI"), and UART interfaces. | ¶39 | col. 2:17-18 |
| wherein the power management commands are provided to the power management unit under control of a processor | HALT and STOP commands are software instructions executed by the CPU. SNOOZE mode is entered from STOP mode based on a trigger event for an enabled peripheral. | ¶39 | col. 6:49-54 |
| sampling the core system block...wherein sampling includes periodically powering the core system block while the processor is in a sleep mode | In SNOOZE mode, which is entered from STOP mode (a sleep mode), a trigger event causes the system to supply the main system clock to a peripheral (e.g., A/D converter), allowing it to perform its function while the CPU remains in a sleep state. The system then reverts to STOP mode to await the next trigger. A timing diagram illustrates the high-speed oscillator activating for the SNOOZE mode period while the CPU remains stopped (Compl. p. 26, Fig. 18-6). | ¶40 | col. 2:38-41 |

Identified Points of Contention (’664 Patent)

  • Scope Questions: The primary dispute may be whether the accused peripherals (A/D converter, UART, CSI) qualify as a "core system block." The patent's specification explicitly distinguishes between "core system blocks" (e.g., voltage reference, power supply monitor) and "application level blocks," listing an Analog-to-Digital Converter (ADC) as an example of the latter (’664 Patent, col. 2:15-28). This raises the question of whether the claim term can be construed to cover the accused functionality.
  • Technical Questions: Does supplying a clock signal to a peripheral, as alleged in SNOOZE mode, constitute "powering" the block as required by the claim? The infringement theory may depend on whether this action involves activating power rails to the block or merely un-gating a clock, which could be argued as a different technical operation.

V. Key Claim Terms for Construction

Patent: ’477 Patent

  • The Term: "program disabling information selection circuit"
  • Context and Importance: This term defines the core logic of the invention. The case may turn on whether Defendant's register-based control scheme, where software sets bits that are later interpreted by system logic, is structurally equivalent to the claimed "selection circuit."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the function of the circuit as outputting information based on two conditions, which could be read broadly to cover any structure performing that function (’477 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The specific embodiment illustrated in Figure 3 shows the circuit (44) implemented with a NAND gate (46), which suggests a hardware logic gate implementation rather than a set of software-readable register bits (’477 Patent, Fig. 3, col. 9:35-41).

Patent: ’664 Patent

  • The Term: "core system block"
  • Context and Importance: Infringement of the ’664 patent hinges on whether the accused peripherals (A/D converter, UART) fall within the scope of this term.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims themselves do not define the term with explicit limitations, and the list of examples could be argued as non-exhaustive.
    • Evidence for a Narrower Interpretation: The specification creates an explicit distinction, stating that "Processing device 100 may include two levels of blocks: core system blocks and application level blocks." It then lists an ADC as an example of an application level block, while listing a power supply monitor and voltage reference as examples of core system blocks (’664 Patent, col. 2:15-28). This passage provides a strong basis for arguing that an ADC is not a "core system block."

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement and contributory infringement for all three patents. The allegations are based on Defendant manufacturing and selling the accused RL78 microcontrollers along with providing technical support, product manuals, advertisements, and other documentation that allegedly instruct and encourage customers to use the products in an infringing manner (Compl. ¶¶29-30, 41-42, 54-55).

Willful Infringement

Willfulness is alleged for all three patents based on alleged pre-suit knowledge. The complaint asserts that Defendant was aware of the patents or was willfully blind to their existence due to "extensive communications" with the prior owner, Monterey Research, LLC, and that Defendant "took affirmative steps to avoid learning of its infringement" (Compl. ¶¶13-15, 31, 43, 56).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: Can the term "core system block," which the ’664 patent specification distinguishes from "application level blocks" like an A/D converter, be construed to cover the accused A/D converter and serial interface peripherals operating in SNOOZE mode?
  • A second key issue will be one of structural and functional equivalence: For the ’477 patent, does the accused microcontroller's use of software-settable register bits that are interpreted by system logic meet the claim limitation of a hardware "selection circuit"? For the ’911 patent, does the accused method of stopping and resetting a timer's counter in response to a mode change constitute "changing the...time out value" as claimed, or is this a fundamentally different technical approach to the problem?
  • A third question will be evidentiary, related to willfulness: What was the specific content of the alleged "extensive communications" between Defendant and the prior patent owner, and what evidence supports the allegation that Defendant took "affirmative steps to avoid learning" about the patents, a key element for a claim of willful blindness?