Signal LLP v. Renesas Electronics Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Signal, LLP (Nevada)
  • Defendant: Renesas Electronics Corporation (Japan)
  • Plaintiff’s Counsel: Nelson Bumgardner Conroy PC; THE LAW OFFICES OF DAVID A. GERASIMOW, P.C.
• Case Identification: 2:26-cv-00093, E.D. Tex., 02/04/2026
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation, which may be sued in any judicial district. The complaint further alleges that Defendant conducts substantial business and has committed acts of infringement in the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including microcontrollers and System-on-Chips (SoCs) that support DDR memory standards, infringe five U.S. patents related to on-die termination and memory controller technologies.
• Technical Context: The technology at issue concerns methods for ensuring signal integrity and data reliability in high-speed memory interfaces, which are fundamental to performance in modern computing, automotive, and embedded systems.
• Key Procedural History: The complaint alleges that Plaintiff’s predecessor-in-interest, Rambus, Inc., and Defendant were parties to a patent license agreement that covered the asserted patents and expired on March 31, 2020. It is further alleged that Rambus provided Defendant with a "Notice of Patent Infringement" on June 4, 2021, specifically identifying the patents-in-suit. The patents were assigned from Rambus to Plaintiff on September 29, 2025. This history may be central to allegations of willful infringement.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,610,459 - Controlling on-die termination in a dynamic random access memory device

• Issued: Dec. 17, 2013

The Invention Explained

• Problem Addressed: In high-speed memory systems with multiple memory modules connected to a shared data path, signals can reflect off the ends of the signal lines, causing interference (Compl. ¶2; ’459 Patent, col. 1:40-45). Conventional on-die termination (ODT) schemes presented a dilemma: terminating the signal line at the selected memory module (the one being written to) could weaken or "unduly attenuate" the incoming data signal, while not terminating it could create an "impedance discontinuity" that also degrades signal quality ’459 Patent, col. 2:25-34
• The Patented Solution: The patent describes a "graduated" on-die termination system that applies different termination impedance values depending on the situation ’459 Patent, abstract For a memory module that is the destination for a data write (the "selected" module), a "soft termination" (higher impedance) is applied to absorb some reflection energy without excessively weakening the signal ’459 Patent, col. 3:30-44 Simultaneously, for a non-selected module on the same data bus, a "hard termination" (lower impedance) is applied to more strongly terminate the signal line stub, preventing reflections ’459 Patent, col. 3:25-30 This selective application of different termination strengths is illustrated in the patent's figures (e.g., ’459 Patent, Fig. 2).
• Technical Importance: This approach provided a more nuanced method for managing signal integrity in multi-module Double Data Rate (DDR) memory systems, enabling higher data rates and greater reliability by mitigating both signal attenuation and reflections ’459 Patent, col. 6:35-40

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶37
• Claim 1 is a method claim for controlling a DRAM device, comprising the essential elements of:
  • Transmitting a write command to the DRAM.
  • Transmitting one or more commands to specify a "digital control value" stored in a register, which indicates a "termination impedance."
  • The termination impedance is coupled to the data interface prior to the DRAM receiving write data.
  • The termination impedance is decoupled from the data interface after the DRAM receives the write data.
• The complaint expressly reserves the right to assert additional claims Compl. ¶39, fn. 8

U.S. Patent No. 8,947,962 - On-die termination of address and command signals

• Issued: Feb. 3, 2015

The Invention Explained

• Problem Addressed: In memory systems using a "fly-by" topology, where command, address, and control (collectively, "RQ") signals are routed sequentially from one memory chip to the next, terminating these signal lines is necessary for signal integrity (’962 Patent, Background). However, conventional termination schemes required extra space on the printed circuit board and consumed "significant power," even when the memory was idle (’439 Patent, col. 1:40-46; ’439 Patent, col. 4:58-62). (Note: The ’439 Patent is a related patent used here for technical context).
• The Patented Solution: The patent proposes a system where the on-die termination for the RQ bus lines can be dynamically controlled and configured with different values for different memory devices on the same bus ’439 Patent, abstract Instead of being statically enabled or disabled, each memory device's ODT circuitry can be programmed via control registers to apply specific, differing impedance values ’439 Patent, abstract ’439 Patent, col. 3:44-55 This allows a memory controller to optimize termination across the entire bus and to disable termination on non-addressed devices or during idle periods to save power ’439 Patent, col. 4:49-62
• Technical Importance: This invention enabled more power-efficient and flexible designs for high-density memory systems by allowing for dynamic, device-specific control over RQ line termination, reducing quiescent power consumption and improving signal integrity ’439 Patent, col. 4:58-62

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶48
• Claim 1 of the related ’439 Patent is a system claim comprising the essential elements of:
  • A memory system with an address and control (RQ) bus.
  • A "first memory device" and a "second memory device" on the bus.
  • The first device includes a control register storing a "first ODT value" for terminating the RQ bus.
  • The second device includes a control register storing a "second ODT value different from the first ODT value" for terminating the RQ bus.
• The complaint expressly reserves the right to assert additional claims Compl. ¶39, fn. 8

U.S. Patent No. 9,092,352 - Memory controller with write data error detection and remediation

• Issued: Jul. 28, 2015

Technology Synopsis

The patent addresses the challenge of maintaining low bit-error rates in high-speed memory interfaces (’352 Patent, col. 1:35-50). It describes a memory controller that dynamically adds error-detection information (such as a CRC code) to outgoing write data, transmits the data, and later receives corresponding error-detection information generated by the memory device itself. The controller compares the original and returned error-detection information to identify transmission errors and can then trigger a remedial action, such as a data retry ’352 Patent, abstract

Asserted Claims

At least Claim 1 Compl. ¶61

Accused Features

The complaint alleges that Defendant’s memory controller integrated circuits, which support various DDR memory standards, infringe by implementing the patented method for write data error detection and remediation Compl. ¶31 Compl. ¶61

U.S. Patent No. 10,056,902 - On-die termination control

• Issued: Aug. 21, 2018

Technology Synopsis

This patent, from the same family as the ’459 Patent, addresses signal integrity in high-speed memory systems (’902 Patent, col. 2:41-50). The invention involves a memory controller that directs a memory IC to apply a first ODT impedance value during the reception of write data, and then switch to a second ODT impedance value after the data has been received. This temporal adjustment of termination strength aims to optimize signal quality throughout the write operation cycle ’902 Patent, abstract

Asserted Claims

At least Claim 1 Compl. ¶72

Accused Features

The complaint accuses Defendant’s DDR-compliant memory controller products of infringing by implementing the claimed method of dynamically controlling ODT impedance values based on the timing of a write operation Compl. ¶31 Compl. ¶72

U.S. Patent No. 10,115,439 - On-die termination of address and command signals

• Issued: Oct. 30, 2018

Technology Synopsis

This patent, from the same family as the ’962 Patent, concerns power consumption and signal integrity on the address and command (RQ) bus in a "fly-by" memory topology ’439 Patent, col. 1:33-46 The solution involves a system where different memory devices on the same bus can be programmed with distinct ODT values via control registers. This allows the system to set different termination impedances for devices at different physical locations on the bus, thereby optimizing signal integrity for the system as a whole ’439 Patent, abstract

Asserted Claims

At least Claim 1 Compl. ¶83

Accused Features

The complaint alleges that Defendant’s memory products infringe by implementing a system where different devices on the same RQ bus utilize different, programmable ODT values for address and command signals Compl. ¶31 Compl. ¶83

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Products" as a broad range of Renesas semiconductors, integrated circuits, microcontrollers (MCUs), microprocessors (MPUs), and Systems-on-Chip (SoCs) that incorporate memory controller circuits supporting one or more Double Data Rate (DDR) memory standards Compl. ¶9 Compl. ¶31 Specific product families are listed in a table, categorized by the DDR standards they support, including DDR3, DDR3L, DDR4, LPDDR4, LPDDR4X, and LPDDR5/5X Compl. ¶34

Functionality and Market Context

The accused products are components that manage the high-speed communication between a central processor and external memory (e.g., DRAM). The complaint alleges these products are used throughout the United States in various applications, including by auto manufacturers Compl. ¶22 Plaintiff alleges that Defendant is a "leading Japanese semiconductor company" and that its revenue and profits have "more than doubled" since the expiration of a prior license agreement that allegedly covered the patents-in-suit Compl. ¶3 Compl. ¶5

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges direct and indirect infringement for each of the five patents-in-suit. For each patent, it states that the accused products "satisfy all claim limitations of at least Claim 1" and incorporates by reference a corresponding claim chart exhibit (Exhibits 1-5) Compl. ¶¶42, 53, 64, 75, 86 As these exhibits were not filed with the complaint, the following analysis is based on the narrative infringement theory.

'459 Patent Infringement Allegations

The complaint alleges that certain of the Accused Products directly infringe at least Claim 1 of the ’459 Patent by practicing the claimed methods for controlling on-die termination in memory devices Compl. ¶37 The core of this allegation appears to be that the accused Renesas controllers and/or the memory systems they operate within apply different termination impedance values at different times or for different modules during write operations, as required by the claims. A potential point of contention may be whether the accused products' termination schemes perform the specific sequence of coupling and decoupling a "termination impedance" that is defined by a "digital control value" as recited in Claim 1. The complaint does not provide sufficient detail for analysis of the specific technical implementation.

'962 Patent Infringement Allegations

The complaint alleges that certain Accused Products infringe at least Claim 1 of the ’962 Patent, which relates to the on-die termination of address and command signals Compl. ¶48 The infringement theory suggests that Renesas products, when used in memory systems, implement an architecture where different memory devices on the same command/address bus are configured with different ODT values. A key question for the infringement analysis will be whether Plaintiff can demonstrate that the accused systems utilize distinct, programmable ODT values stored in registers on different memory devices, as the claims of the patent family require. The complaint does not provide sufficient detail for analysis of this architectural feature.

V. Key Claim Terms for Construction

For the ’459 Patent

• The Term: "termination impedance"
• Context and Importance: This term is the central object of Claim 1; the entire method is about controlling it. Its construction will determine what types of on-die electrical loads and control mechanisms fall within the scope of the claim. Practitioners may focus on this term because the dispute could turn on whether the accused devices' termination methods, which may be complex, meet the definition of the claimed "termination impedance."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification refers generally to "termination loads" and "load elements" without restriction to a particular type of component, suggesting the term could be construed broadly to cover various ways of presenting an impedance to a signal line ’459 Patent, col. 4:45-48
  • Evidence for a Narrower Interpretation: The detailed description and figures primarily discuss distinct resistive loads, denoted "R1" and "R2," where one provides a "hard termination" and the other a "soft termination" ’459 Patent, Fig. 2 ’459 Patent, col. 5:13-16 This could support an argument that "termination impedance" is limited to discrete, selectable resistive values.

For the ’962 Patent (and related ’439 Patent)

• The Term: "second ODT value different from the first ODT value"
• Context and Importance: The inventive concept described in the asserted claim of the patent family hinges on the differentiation of ODT values between memory devices on the same bus. The definition of "different" will be critical to determining infringement. The question is whether any non-identical programmed value is "different," or if a more substantial, technologically distinct difference is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself does not quantify the required difference, which may support a construction where any non-identical programmed setting for the ODT value on two separate devices meets the limitation ’439 Patent, claim 1
  • Evidence for a Narrower Interpretation: The specification provides examples of distinct termination modes, such as "Nominal Z," "Alternate Z," and "High Z," which are selected via control pins ’439 Patent, Fig. 5 This embodiment of discrete, predefined levels could be used to argue that "different" requires more than a minor variation and implies a selection between functionally distinct termination modes.

VI. Other Allegations

• Indirect Infringement: For each patent, the complaint alleges induced infringement. The stated basis is that Renesas provides products along with "instructive materials," "user manuals," "technical documentation," partner programs, and customer support that allegedly direct and encourage customers and end-users to operate the products in an infringing manner (e.g., Compl. ¶¶40-41; Compl. ¶¶51-52).
• Willful Infringement: The complaint makes allegations of willful infringement for all asserted patents. The primary bases for this claim are the alleged pre-suit knowledge stemming from (1) the prior patent license agreement between Defendant and Plaintiff's predecessor, Rambus, which allegedly covered the patents, and (2) a specific "Notice of Patent Infringement" that Rambus allegedly sent to Renesas on June 4, 2021, identifying the patents and accused products Compl. ¶¶3-4, 44, 55

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of intent and damages: given the alleged history of a prior licensing relationship and a subsequent explicit notice of infringement, a key question for the court will be how to characterize Defendant’s conduct after the license expired. The resolution of this issue will be a primary driver of potential liability for willful infringement and enhanced damages.
• A key evidentiary question will be one of technical proof: the complaint alleges that a wide array of sophisticated semiconductor products infringe five distinct patents, but it does so without providing public technical evidence, relying instead on referenced exhibits. The case will likely turn on whether Plaintiff can produce, through discovery and expert analysis, concrete evidence mapping the specific, complex operations of the accused memory controllers to the discrete limitations recited in the asserted claims.