DCT

4:19-cv-00733

Vantage Micro LLC v. Texas Instruments Inc

Key Events

Complaint

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: Vantage Micro LLC (Delaware)
- Defendant: Texas Instruments Incorporated (Delaware)
- Plaintiff’s Counsel: DEVLIN LAW FIRM LLC
Case Identification: 4:19-cv-00733, E.D. Tex., 10/07/2019
Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant Texas Instruments (TI) maintains a regular and established place of business in the district, including a large semiconductor fabrication facility in Sherman, Texas, and because acts of infringement allegedly occurred there.
Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including various processors, microcontrollers, and systems-on-a-chip, infringe four patents related to memory controller architecture, display interface detection, and fault detection in semiconductor manufacturing.
Technical Context: The technologies at issue are fundamental to the design and manufacture of modern integrated circuits, addressing performance and reliability challenges in multi-component systems.
Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement for three of the four asserted patents on May 14, 2019, nearly five months prior to filing the lawsuit. No other prior litigation, licensing, or administrative proceedings are mentioned.

Case Timeline

Date	Event
1999-07-02	Earliest Priority Date for U.S. Patent No. 9,959,593
1999-08-23	Earliest Priority Date for U.S. Patent No. 6,678,838
1999-10-29	Earliest Priority Date for U.S. Patent No. 6,546,508
1999-11-02	Earliest Priority Date for U.S. Patent No. 7,414,606
2003-04-08	U.S. Patent No. 6,546,508 Issued
2004-01-13	U.S. Patent No. 6,678,838 Issued
2008-08-19	U.S. Patent No. 7,414,606 Issued
2018-05-01	U.S. Patent No. 9,959,593 Issued
2019-05-14	Alleged notice of infringement for '838, '606, '593 Patents
2019-10-07	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,678,838 - "Method to Track Master Contribution Information in a Write Buffer"

The Invention Explained

Problem Addressed: In complex integrated circuits with multiple processing units (or "masters") like a CPU and a graphics processor all writing to a shared memory, developers have difficulty determining the source of specific data during debugging because a "write buffer" obscures the originating master (’838 Patent, col. 2:46-59).
The Patented Solution: The invention adds "master trace bits" to the write buffer architecture. When a master writes data, the system records information identifying that master in the trace bits, which are stored alongside the data. These trace bits are made externally accessible, allowing a developer using a logic analyzer or other debug tool to see exactly which master contributed the data for any given memory write cycle (’838 Patent, Abstract; col. 2:7-25).
Technical Importance: This technique provides crucial visibility for debugging complex multi-master systems-on-a-chip (SoCs), a design approach that became increasingly prevalent for integrating functionality and improving performance (’838 Patent, col. 2:56-59).

Key Claims at a Glance

The complaint asserts independent Claim 11 (Compl. ¶23, 25).
The essential elements of Claim 11, a method claim, are:
- receiving data into a buffer;
- examining grant signals of a master which originated the data; and
- storing master contribution information in the buffer to associate the master with the data.
- wherein the buffer is a first-in-first-out (FIFO) buffer.
The complaint reserves the right to assert other claims (Compl. ¶23).

U.S. Patent No. 7,414,606 - "Method and Apparatus for Detecting a Flat Panel Display Monitor"

The Invention Explained

Problem Addressed: The patent addresses the inconvenience of older systems that required a computer to be fully powered down before an external flat panel display (FPD) could be connected for it to be recognized (’606 Patent, col. 1:17-24).
The Patented Solution: The invention describes a system that enables "hot-plugging" a display. It utilizes a dedicated "monitor detect pin" on the display connector that is monitored by a detection circuit. When a display is plugged in, the voltage on this pin changes, which triggers a system interrupt. This interrupt notifies the host system’s software that a new display is present, allowing it to automatically enable the appropriate drivers and output a video signal without a reboot (’606 Patent, Abstract; col. 2:45-56).
Technical Importance: This method provides the technical underpinning for the "plug-and-play" user experience for external monitors that is now ubiquitous (’606 Patent, col. 1:26-28).

Key Claims at a Glance

The complaint asserts independent Claim 6 (Compl. ¶36, 38).
The essential elements of Claim 6, a method claim, are:
- monitoring one pin of a connector coupled to a flat panel display;
- asserting an output signal to indicate the one pin is in a first state; and
- receiving the output signal at a display engine.
The complaint reserves the right to assert other claims (Compl. ¶36).

Multi-Patent Capsule: U.S. Patent No. 6,546,508

Patent Identification: U.S. Patent No. 6,546,508, "Method and Apparatus for Fault Detection of a Processing Tool in an Advanced Process Control (APC) Framework," Issued April 8, 2003.
Technology Synopsis: This patent describes a system to reduce costly delays in identifying faults during semiconductor manufacturing. The invention outlines a framework that receives operational state data from a fabrication tool, analyzes it in a dedicated fault detection unit to see if it deviates from a known-good model, and performs a predetermined action, such as halting production, if a fault is found (’508 Patent, Abstract; col. 1:31-44).
Asserted Claims: Independent Claim 1 (Compl. ¶50).
Accused Features: TI's alleged use of "Inficon FabGuard® FDC or a similar system" within its fabrication facilities to produce semiconductor products that are subsequently imported into or sold in the U.S. (Compl. ¶50, 52, 54).

Multi-Patent Capsule: U.S. Patent No. 9,959,593

Patent Identification: U.S. Patent No. 9,959,593, "Memory Controller Having Plurality of Channels that Provides Simultaneous Access to Data When Accessing Unified Graphics Memory," Issued May 1, 2018.
Technology Synopsis: The patent addresses performance limitations in systems using a "unified memory" architecture, where system operations (CPU) and graphics operations compete for access to the same memory. The invention discloses a memory controller with multiple channels that can provide parallel, simultaneous memory access for the CPU and other clients (e.g., a graphics engine), thereby improving overall data throughput and system performance (’593 Patent, Abstract; col. 2:56-65).
Asserted Claims: Independent Claim 1 (Compl. ¶60).
Accused Features: TI processors and controllers (e.g., AM5K2xxx, OMAP series) that allegedly contain a memory controller for providing simultaneous data access for CPU and client requests to a unified system/graphics memory (Compl. ¶60).

III. The Accused Instrumentality

Product Identification

The complaint accuses a broad range of TI semiconductor products. For the ’838 Patent, the lead accused product is the Keystone II System-on-Chip (SoC) (Compl. ¶25). For the ’606 Patent, the lead accused product is the DRA71x processor, among a wider family of integrated circuits, receivers, and processors that support display interfaces (Compl. ¶36, 38).

Functionality and Market Context

The complaint alleges the Keystone II SoC and related products are complex electronic components that incorporate multiple "masters," such as processor cores and graphics processors, which write data to a shared memory (Compl. ¶23). It further alleges that TI's own documentation instructs developers to use a "Master/Slave model" when programming these chips, which Vantage Micro contends involves the infringing method (Compl. ¶28).
The complaint alleges the DRA71x processor and other accused products are components that "detect, or support the detection of, monitors" through standard interfaces like HDMI, DisplayPort, and DVI (Compl. ¶36). The infringement theory is based on allegations that TI provides technical documentation, such as a reference manual for the DRA71x processor, that instructs customers on how to configure and use these products with such display connections (Compl. ¶41).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits detailing its infringement theories. The narrative infringement allegations are summarized below.

’838 Patent Infringement Allegations

The complaint alleges that TI’s Keystone II SoC products directly infringe one or more claims, including method Claim 11 (Compl. ¶23). The narrative theory is that these SoCs contain multiple processing masters that write to shared memory, and that any use of these devices "necessarily practices the method of Claim 11" (Compl. ¶25). The complaint states that a detailed chart showing how the Keystone II SoC meets each element of Claim 11 is attached as Exhibit 5, which is not provided in the filed document (Compl. ¶25).

’606 Patent Infringement Allegations

The complaint alleges that TI products, including the DRA71x processor, infringe one or more claims, including method Claim 6, by being made, used, or sold in the U.S. (Compl. ¶36). The infringement theory is that these products are designed to detect or support the detection of monitors using standard connection interfaces. The complaint asserts that "[e]ach and every element of Claim 6 is found in this product as shown in Exhibit 6," which is also not provided (Compl. ¶38). The infringement theory appears to rely on the inherent functionality of the accused components when used as intended in a larger system.

Identified Points of Contention

Scope Questions: A central question for the method claims (’838 and ’606 patents) will be whether TI, as a seller of components, can be found to have directly performed the claimed method steps. The analysis may focus on whether the accused processors’ functions (e.g., supporting a master/slave model or being configurable for HDMI) constitute the specific actions of "examining grant signals" (’838 patent) or "monitoring one pin" and "asserting an output signal" (’606 patent).
Technical Questions: The complaint’s allegations are based on high-level product functions and references to technical manuals. A key technical question will be what evidence demonstrates that the accused SoCs internally operate in a way that maps to the specific claim limitations. For the ’838 patent, this may involve whether the accused "Master/Slave model" actually requires "examining grant signals" and "storing master contribution information" as recited in Claim 11.

V. Key Claim Terms for Construction

The Term: "master contribution information" (’838 Patent, Claim 11)
Context and Importance: This term is the invention's core concept, defining what must be stored to identify the source of a memory write. Its construction is critical because it will determine the type and format of data required to prove infringement. Practitioners may focus on this term to dispute whether the accused devices store any "information" that sufficiently associates a "master" with the data as claimed.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the goal broadly as enabling a debugger to "identify which master wrote to DRAM at a particular address" and to "determine which master wrote to system memory," suggesting any data achieving this purpose could qualify (’838 Patent, col. 2:21-23, 63-64).
- Evidence for a Narrower Interpretation: The patent’s detailed embodiment describes dedicated "master trace bits" (e.g., WB_MSTR[2:0]) that are coupled to specific CPU_GNT and PCI_GNT signals (’838 Patent, col. 8:1-2, Fig. 5). A party could argue this specific implementation limits the term to a set of dedicated bits explicitly representing master grant signals.
The Term: "monitoring one pin" (’606 Patent, Claim 6)
Context and Importance: This active verb is the first step of the claimed method. The infringement analysis will likely turn on whether providing a processor with the capability to read a pin status is equivalent to performing the act of "monitoring." This distinction is critical for establishing direct infringement by the seller of a component.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes the invention functionally, stating that "a monitor detect pin is monitored by a detect circuit," which could be interpreted to cover any circuit that performs this function, however implemented (’606 Patent, col. 2:46-47).
- Evidence for a Narrower Interpretation: The figures and detailed description depict a specific "detect module 210" that performs the monitoring, separate from other system components (’606 Patent, Fig. 1). A defendant could argue that "monitoring" requires an active, continuous, or dedicated process as embodied by this module, rather than a general-purpose I/O function of a processor.

VI. Other Allegations

Indirect Infringement: The complaint alleges both induced infringement (§ 271(b)) and contributory infringement (§ 271(c)) for the ’838, ’606, and ’593 patents (Compl. ¶26, 29, 39, 43, 63, 66). The allegations are predicated on TI providing customers with the accused components along with technical documentation, user manuals, and support that allegedly instruct and encourage users to operate the products in an infringing manner (e.g., by using a "Master/Slave model" or configuring a processor for HDMI use) (Compl. ¶27-28, 41, 65). For the ’508 patent, the complaint alleges infringement under § 271(g) by importing into the U.S. products made overseas using the patented process (Compl. ¶54).
Willful Infringement: Willfulness is alleged for all four patents. For the ’838, ’606, and ’593 patents, the allegation is based on TI’s continued infringement after receiving alleged actual notice on May 14, 2019 (Compl. ¶32, 46, 70). For the ’508 patent, willfulness is predicated on notice occurring upon the filing and service of the complaint itself (Compl. ¶49).

VII. Analyst’s Conclusion: Key Questions for the Case

A central issue across the asserted method claims (’838, ’606, ’508, ’593) will be one of liability for process infringement: can TI, as a seller of semiconductor components, be held directly liable for infringing method claims that appear to describe the operation of a larger system or a manufacturing process? This question will likely shift focus to the sufficiency of the indirect infringement allegations and the evidence of TI's specific intent to encourage its customers' infringing acts.
A key evidentiary question will be one of technical proof: the complaint relies heavily on product-level descriptions and references to technical manuals. The case may turn on whether Plaintiff can produce evidence from discovery that the internal architecture and micro-operations of TI's complex SoCs perform the specific, granular steps recited in the claims, such as the "examining grant signals" of the ’838 patent or the comparison to a "fault model" in the ’508 patent.
The case also raises a question of infringement under 35 U.S.C. § 271(g): for the ’508 patent, which claims a method of fault detection in manufacturing, a primary issue will be whether Plaintiff can establish that TI’s overseas fabrication facilities utilize a process that meets all limitations of Claim 1, and that semiconductor products manufactured by that process are subsequently imported into the United States for sale or use.