DCT
4:22-cv-00819
Bell Semiconductor LLC v. Rockchip Electronics Co Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Rockchip Electronics Co., Ltd. (China)
- Plaintiff’s Counsel: Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 4:22-cv-00819, E.D. Tex., 09/23/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign resident who may be sued in any judicial district and has committed acts of infringement in, and directs products to, the Eastern District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s circuit design methodologies, used in the production of semiconductor chips like the RK805-2, infringe two patents related to improving manufacturing planarity and performance through optimized placement of "dummy fill" material.
- Technical Context: The technology addresses methods within the semiconductor fabrication process for adding non-functional "dummy" metal to chip layers to ensure a uniform surface density, which is critical for the success of Chemical Mechanical Planarization (CMP).
- Key Procedural History: Plaintiff asserts ownership of the patents-in-suit by assignment, noting they are part of a portfolio with a lineage tracing back to Bell Labs, Lucent Technologies, and LSI. The complaint references an expert declaration supporting its infringement allegations. Notably, after the filing of this complaint, U.S. Patent No. 7,007,259 underwent an ex parte reexamination, with a certificate issuing on July 5, 2023, confirming the patentability of all asserted independent claims. This may strengthen the patent's presumption of validity.
Case Timeline
| Date | Event |
|---|---|
| 2000-01-18 | ’807 Patent Priority Date |
| 2002-08-20 | ’807 Patent Issue Date |
| 2003-07-31 | ’259 Patent Priority Date |
| 2006-02-28 | ’259 Patent Issue Date |
| 2022-09-23 | Complaint Filing Date |
| 2023-07-05 | ’259 Patent Reexamination Certificate Issued |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,007,259 - "Method for Providing Clock-Net Aware Dummy Metal Using Dummy Regions," issued February 28, 2006
The Invention Explained
- Problem Addressed: The patent’s background section describes that prior art methods for inserting dummy metal often required a large "stay-away" distance from timing-sensitive clock nets ('259 Patent, col. 2:1-6). This made it difficult or impossible to add enough dummy metal to meet minimum density requirements in a single pass, forcing an "involved, iterative process" that could delay the design schedule ('259 Patent, col. 2:10-18; Compl. ¶25).
- The Patented Solution: The invention proposes a software-implemented method that "minimizes the negative timing impact of dummy metal on clock nets, while at the same time achieving minimum density in a single run" ('259 Patent, col. 2:19-23). It achieves this by identifying all available "dummy regions" for metal insertion and then prioritizing them so that the regions located adjacent to critical clock nets are filled with dummy metal last ('259 Patent, Abstract; Compl. ¶27). This ensures that less critical areas are filled first, often satisfying the density requirement before any metal needs to be placed near the sensitive clock nets.
- Technical Importance: This "clock-net aware" approach provided a more efficient method for meeting manufacturing density rules without degrading the timing performance of a chip, a critical trade-off in semiconductor design ('259 Patent, col. 6:11-15; Compl. ¶28).
Key Claims at a Glance
- The complaint asserts independent claim 1 (a method) and notes the patent also contains independent claims directed to a computer-readable medium (Compl. ¶27).
- Independent Claim 1 requires:
- A method for inserting dummy metal into a circuit design that includes a plurality of objects and clock nets.
- (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions, and
- (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.
- The complaint alleges infringement of "one or more claims," reserving the right to assert dependent claims (Compl. ¶42).
U.S. Patent No. 6,436,807 - "Method for Making an Interconnect Layer and a Semiconductor Device Including the Same," issued August 20, 2002
The Invention Explained
- Problem Addressed: The patent explains that non-uniform density of metal features on a semiconductor layer prevents effective planarization via CMP, causing "protrusions" or "dishing" that can lead to defects ('807 Patent, col. 1:36-42, 1:67-2:8). Conventional algorithms to fix this would add dummy fill based on a "predetermined set density," which often resulted in adding unnecessary metal, thereby increasing parasitic capacitance and slowing the device ('807 Patent, col. 2:22-33; Compl. ¶3).
- The Patented Solution: The invention describes a method for creating a layout that first determines the existing "active interconnect feature density" for various regions of the chip ('807 Patent, Abstract). It then adds dummy fill features to each region specifically to obtain a "desired density," which avoids adding unnecessary fill ('807 Patent, col. 6:63-65). A key aspect is "defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias" to ensure the added features effectively facilitate planarization ('807 Patent, col. 7:1-5; Compl. ¶5).
- Technical Importance: This method provided a more precise way to achieve uniform layer density for manufacturing, while simultaneously minimizing the negative performance impact of parasitic capacitance from unneeded dummy fill ('807 Patent, col. 5:9-12; Compl. ¶6).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶35).
- Independent Claim 1 requires:
- A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization.
- (a) determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout.
- (b) adding dummy fill features to each layout region to obtain a desired density of active interconnect features and dummy fill features, where the adding step comprises "defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a dielectric layer to be deposited over the interconnect layer."
- The complaint reserves the right to assert other claims from the patent (Compl. ¶55).
III. The Accused Instrumentality
- Product Identification: The complaint identifies the "Accused Processes" as the infringing instrumentalities. These are defined as the circuit design methodologies and tools (e.g., from Cadence, Synopsys, and/or Siemens) that Defendant Rockchip employs to design semiconductor devices (Compl. ¶43, ¶56). The RK805-2 chip is identified as an exemplary product manufactured using these processes (Compl. ¶42, ¶55).
- Functionality and Market Context: The Accused Processes are alleged to be software-based design methods used to automatically insert dummy metal into a chip layout to meet manufacturing requirements (Compl. ¶43). The complaint alleges that these processes perform the specific steps recited in the patents-in-suit, such as prioritizing fill regions and calculating fill amounts based on specific parameters (Compl. ¶44-45, ¶57-59). Plaintiff alleges that Rockchip derives substantial revenues from products made using these processes (Compl. ¶20).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’259 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions... | Rockchip allegedly uses a design tool (e.g., Cadence, Synopsys, Siemens) to identify free spaces on each layer of its RK805-2 device's circuit design. | ¶44 | col. 4:35-39 |
| (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last... | Rockchip's design process allegedly assigns a "high cost" to adding metal fill near clock nets and a "lower cost" to adding it elsewhere, which purportedly fills the dummy regions adjacent to clock nets last. | ¶45 | col. 5:35-48 |
- Identified Points of Contention:
- Scope Questions: A central question will be whether Rockchip's alleged use of a "cost"-based system for placing dummy fill meets the claim limitation of "prioritizing... such that the dummy regions... are filled with dummy metal last." The court may need to determine if "last" requires being in the absolute final group to be filled, or if a system that strongly de-prioritizes these regions is sufficient.
- Technical Questions: What evidence demonstrates that Rockchip's application of general-purpose third-party design tools is specifically configured to implement the "fill last" methodology? The infringement allegation is made on "information and belief" and will likely depend on discovering Rockchip's internal design rules and tool configurations.
’807 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) determining an active interconnect feature density for each of a plurality of layout regions... | Rockchip's design tool allegedly determines the active interconnect feature density for layout regions of its RK805-2 chip design. | ¶57 | col. 5:53-57 |
| (b) adding dummy fill features to each layout region to obtain a desired density... the adding comprising defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias... | Rockchip's design tool allegedly adds dummy fill to obtain a desired density, and this process comprises defining a minimum fill dimension based on a dielectric layer deposition bias for the subsequent layer. | ¶58-59 | col. 7:1-5 |
- Identified Points of Contention:
- Technical Questions: The key dispute will likely focus on the most specific limitation: does Rockchip’s process actually "defin[e] a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias"? This requires a link between a software design rule and a specific physical manufacturing parameter. The case may turn on evidence showing whether Rockchip's design rules explicitly or implicitly account for this physical bias, or if they are based on more generic, abstract rules.
V. Key Claim Terms for Construction
For the ’259 Patent:
- The Term: "prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last"
- Context and Importance: This phrase captures the core inventive concept. The infringement allegation rests on a "cost" assignment system achieving this result (Compl. ¶45). Practitioners may focus on this term because its interpretation will determine whether a relative de-prioritization (via cost) is equivalent to the claim's requirement of being filled "last."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes implementing the prioritization by calculating a "Timing Factor" and then sorting a list in ascending order ('259 Patent, col. 5:35-42). This could support an argument that any mechanism, including a cost-based one, that results in an ordered process where clock-net regions are handled after others falls within the claim scope.
- Evidence for a Narrower Interpretation: The plain language "filled with dummy metal last" could be argued to require that these regions are the absolute final areas to receive dummy fill, if any is needed. The patent's stated goal of achieving density "in a single run" ('259 Patent, col. 2:22) could be used to argue for a strict, sequential process that the term "last" implies.
For the ’807 Patent:
- The Term: "based upon a dielectric layer deposition bias"
- Context and Importance: This term connects the software-based design method to a specific, physical characteristic of the manufacturing process. The viability of the infringement case hinges on whether Rockchip's accused design process uses rules that are "based upon" this physical property.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification explains the physical meaning of the bias (e.g., protrusions being wider or narrower than the underlying feature) ('807 Patent, col. 3:13-24). A party could argue that any design rule that accounts for these known physical deposition effects is "based upon" the bias, even if the term itself is not used as a direct input.
- Evidence for a Narrower Interpretation: The patent provides a specific example where the required dimension of a dummy fill feature is calculated as being "at least twice an absolute value of the negative dielectric layer deposition bias" ('807 Patent, col. 6:20-23). This suggests a direct, quantitative relationship, and a party could argue that "based upon" requires such a direct numerical input or calculation, not merely a qualitative consideration of deposition effects.
VI. Other Allegations
- Indirect Infringement: The complaint includes general allegations of indirect infringement for both patents (Compl. ¶47, ¶61). However, it does not plead specific facts to support theories of induced or contributory infringement, such as knowledge and intent demonstrated through user manuals, instructions to third parties, or the provision of components with no substantial non-infringing use. The primary allegations are for direct infringement by Rockchip's own use of the accused processes.
- Willful Infringement: For both patents, the complaint alleges that Rockchip's infringement is "exceptional" and requests attorneys' fees pursuant to 35 U.S.C. § 285 (Compl. ¶48, ¶62). While the word "willful" is not explicitly used in the individual counts, this allegation serves as the basis for a willfulness claim. The complaint does not allege any facts regarding pre-suit knowledge of the patents.
VII. Analyst’s Conclusion: Key Questions for the Case
Evidentiary Proof of Practice: A central issue will be one of process implementation: Can Plaintiff produce evidence from discovery to demonstrate that Defendant's use of general-purpose, third-party electronic design automation (EDA) tools is specifically configured to perform the highly detailed steps of the asserted claims? This includes proving the "fill last" prioritization of the ’259 patent and, most critically, the dependency on a "dielectric layer deposition bias" for the ’807 patent.
Claim Construction and Technical Equivalence: The outcome may depend on a question of definitional precision: For the '807 patent, will "based upon a... bias" be construed to require a direct, quantitative input of that physical parameter, or can it be satisfied by a design rule that indirectly accounts for the known effects of deposition? For the ’259 patent, does "filled... last" mandate an absolute final action in a sequence, or can it be met by a relative "costing" system that merely de-prioritizes certain regions?
Impact of Reexamination: A key procedural factor will be the effect of the '259 patent's reexamination, which was successfully concluded after the suit was filed. How will the fact that the U.S. Patent and Trademark Office confirmed the patentability of the asserted claims, in light of new prior art, influence the court’s view of the patent's validity and potentially impact settlement leverage?