DCT
4:22-cv-00962
Bell Semiconductor LLC v. Rockchip Electronics Co Ltd
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Rockchip Electronics Co., Ltd. (China)
- Plaintiff’s Counsel: McKool Smith, P.C.; Devlin Law Firm LLC
- Case Identification: 4:22-cv-00962, E.D. Tex., 11/14/2022
- Venue Allegations: Plaintiff alleges that venue is proper because the Defendant is a foreign corporation that may be sued in any judicial district, and further alleges that Defendant commits acts of infringement and conducts substantial business within the Eastern District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s processes for designing semiconductor chips infringe patents related to methodologies for efficiently implementing design changes and for reducing electrical interference in multi-layered circuits.
- Technical Context: The technology addresses critical efficiency and performance bottlenecks in the design and fabrication of modern, complex integrated circuits (ICs), where small optimizations can significantly impact time-to-market and device performance.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2004-11-17 | ’760 Patent Priority Date |
| 2004-12-17 | ’626 Patent Priority Date |
| 2007-06-12 | ’626 Patent Issue Date |
| 2008-07-08 | ’760 Patent Issue Date |
| 2022-11-14 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - "Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows," Issued June 12, 2007
The Invention Explained
- Problem Addressed: The patent’s background section describes that prior methods for implementing an engineering change order (ECO) in an IC design were highly inefficient. They required design tools to re-process the entire circuit design, even for a minor change, resulting in a "typical turnaround time" of "about one week" regardless of the change’s size (Compl. ¶29; ’626 Patent, col. 2:15-22, 2:37-44).
- The Patented Solution: The invention proposes a method to isolate the ECO’s impact. It involves creating a "window"—a defined area smaller than the entire circuit—that encloses the change. Design processes like routing are then performed only within this localized window. The results are subsequently merged back into a copy of the full design, generating a revised circuit without the need to re-run time-consuming processes on unaffected areas (’626 Patent, Abstract; col. 3:18-23).
- Technical Importance: This windowing technique was designed to yield "significant savings in the resources required to perform routing, design rule check verification, net delay calculation, and parasitic extraction," thereby shortening the overall design timeline for complex ICs (Compl. ¶30; ’626 Patent, col. 3:18-23).
Key Claims at a Glance
- The complaint asserts infringement of at least independent Claim 1 (Compl. ¶51).
- Essential elements of Claim 1 include:
- Receiving as input an integrated circuit design and an engineering change order.
- Creating at least one "window" that encloses the change and defines an area "less than an entire area of the integrated circuit design."
- Performing "incremental routing" only for each net enclosed by the window.
- Replacing the corresponding area in a copy of the design with the results of the incremental routing.
- Generating the revised integrated circuit design as output.
U.S. Patent No. 7,396,760 - "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits," Issued July 8, 2008
The Invention Explained
- Problem Addressed: To ensure surface uniformity for manufacturing, IC fabrication uses "dummy fill" in sparse areas. The patent explains that when dummy fill on successive layers overlaps, it creates unwanted "interlayer bulk capacitance," which can slow signal transmission and degrade performance. Prior art tools allegedly failed to account for these interlayer effects, focusing only on effects within a single layer (Compl. ¶¶8-9; ’760 Patent, col. 1:62-2:6).
- The Patented Solution: The invention describes a method of "intelligent dummy fill placement" that analyzes successive layers as a pair. It identifies areas of potential overlap for dummy fill between the two layers and then "re-arrang[es]" the fill features to minimize this overlap, thereby reducing the harmful interlayer capacitance (’760 Patent, Abstract; col. 2:7-13).
- Technical Importance: By minimizing unwanted interlayer capacitance, the method aims to improve the speed and performance of the final IC, while still achieving the uniform surface density required for the chemical-mechanical planarization (CMP) process (Compl. ¶11).
Key Claims at a Glance
- The complaint asserts infringement of at least independent Claim 1 (Compl. ¶65).
- Essential elements of Claim 1 include:
- Obtaining layout information for an IC with multiple layers.
- Obtaining a "first dummy fill space" for a first layer and a "second dummy fill space" for a successive second layer.
- Determining an "overlap" between the first and second dummy fill spaces.
- "Minimizing the overlap by re-arranging" the dummy fill features in both spaces.
- The dummy fill spaces include non-signal carrying lines.
III. The Accused Instrumentality
- Product Identification: The complaint identifies the Rockchip RK805-2 semiconductor chip as an exemplary "Accused Product" (Compl. ¶1). The infringement allegations are directed at the "Accused Processes"—the design methodologies Rockchip allegedly uses to create this and other semiconductor devices (Compl. ¶52).
- Functionality and Market Context: The complaint alleges that Rockchip utilizes a variety of commercial electronic design automation (EDA) tools from vendors such as Cadence, Synopsys, and/or Siemens to implement the accused design and fabrication processes (Compl. ¶¶52, 66). The complaint alleges that the patented technologies provide "significant commercial value" by improving design efficiency and final product performance, but does not provide specific market details for the RK805-2 chip itself (Compl. ¶¶32, 11).
No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; | Rockchip's Accused Processes allegedly perform parasitic extraction and design rule checks "only for each net in the IC design enclosed by the window defining the ECO." | ¶¶53-54 | col. 1:31-38 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | Rockchip allegedly uses a design tool to "perform a method for only routing the nets affected by the ECO." | ¶52 | col. 1:39-42 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; | The Accused Processes allegedly perform the step of "merging that changed area into the overall circuit layout as required by claim 1." | ¶52 | col. 1:43-48 |
- Identified Points of Contention:
- Scope Questions: Does Rockchip's alleged use of third-party commercial EDA software constitute "using" the patented method under 35 U.S.C. § 271(a)? The case may turn on whether Rockchip directs the tools to operate in the specific manner claimed, or whether it is merely a passive user of a standard tool function.
- Technical Questions: What evidence demonstrates that Rockchip's process performs incremental routing and other checks only for nets within the defined window, as strictly required by the claim? Further, does the process replace an area in a copy of the design, or does it modify the original design directly, potentially creating a technical distinction from the claim language?
’760 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (d) determining an overlap between the first dummy fill space and the second dummy fill space; and | The Accused Processes allegedly determine overlap in successive layers as part of a process to "stagger the dummy fill... so as to minimize the interlayer bulk capacitance." | ¶66 | col. 8:23-26 |
| (e) minimizing the overlap by re-arranging a plurality of first dummy fill features and a plurality of second dummy fill features; | Rockchip allegedly "employs a variety of design tools... to rearrange dummy fill to minimize its overlap in successive layers." | ¶66 | col. 8:30-32 |
| (f) wherein the first dummy fill space includes non-signal carrying lines on the first layer and the second dummy fill space includes non-signal carrying lines on the second layer. | Rockchip's processes allegedly "implement dummy fill functionality in a timing-aware fashion," which inherently involves non-signal carrying features. | ¶67 | col. 2:32-34 |
- Identified Points of Contention:
- Scope Questions: What is the scope of "re-arranging"? Does it encompass any modification that results in less overlap, or must it be a specific type of rearrangement, such as the "checkerboard pattern" described as an embodiment in the patent? (c.f. ’760 Patent, col. 8:50-52).
- Technical Questions: Does the accused process specifically analyze "successive layers" as a pair to minimize "interlayer" capacitance, as taught by the patent? Or does it employ a more generic density optimization algorithm that may incidentally reduce overlap but is not directed at the specific interlayer problem the patent claims to solve?
V. Key Claim Terms for Construction
For the ’626 Patent:
- The Term: "window"
- Context and Importance: This term is the central feature of the ’626 Patent. Its construction will determine whether the method by which the accused processes isolate design changes falls within the scope of the claims. Practitioners may focus on this term because its boundaries—whether purely functional or tied to a specific implementation—are critical to the infringement analysis.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification provides a broad definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 4:59-62).
- Evidence for a Narrower Interpretation: The patent also describes a specific method for creating the window, involving identifying port instances and calculating bounding boxes (’626 Patent, FIG. 3; col. 4:56-5:12). A party could argue the term should be limited by these disclosed steps.
For the ’760 Patent:
- The Term: "re-arranging"
- Context and Importance: This is the primary active step in Claim 1 of the ’760 Patent. The definition of this term is critical because it dictates what kind of modification to the dummy fill placement constitutes infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The plain language of the claim, "re-arranging a plurality of first dummy fill features and a plurality of second dummy fill features," does not specify a particular method of rearrangement, suggesting any modification to minimize overlap could suffice (’760 Patent, col. 6:16-19).
- Evidence for a Narrower Interpretation: The specification repeatedly highlights a "checkerboard pattern" as a preferred embodiment for avoiding overlap (’760 Patent, col. 8:40-45, 8:50-52). A party may argue that "re-arranging" should be construed to require an offset pattern similar to the checkerboard embodiment, rather than just any adjustment.
VI. Other Allegations
- Willful Infringement: The complaint does not use the term "willful," but it alleges that Rockchip's infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶¶58, 71). The complaint alleges that Rockchip "has and continues to" infringe, which may support a claim for enhanced damages based on post-suit conduct, but no facts alleging pre-suit knowledge of the patents are provided (Compl. ¶¶57, 70).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of infringing use: does Rockchip's alleged use of third-party commercial design software to create its products constitute "using" the patented methods as claimed, or can it successfully argue that it is merely operating a tool and not performing, controlling, or directing all the specific steps required by the patent claims?
- A key evidentiary question will be one of technical specificity: can Plaintiff provide evidence that Rockchip's design processes perform the precise functions claimed—such as the '626 patent's isolation of all subsequent routing and verification within a "window," and the '760 patent's "re-arranging" of dummy fill driven specifically by minimizing interlayer capacitance—or is there a fundamental mismatch in technical operation?