DCT
4:23-cv-00069
Bell Semiconductor LLC v. ams Sensors USA Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: ams Sensors USA Inc. (Texas) and ams-OSRAM AG (Austria)
- Plaintiff’s Counsel: McKool Smith, P.C.
- Case Identification: 4:23-cv-00069, E.D. Tex., 01/25/2023
- Venue Allegations: Venue is alleged to be proper in the Eastern District of Texas because Defendant ams Sensors USA Inc. has a regular and established place of business within the district.
- Core Dispute: Plaintiff alleges that Defendant’s methodologies for designing integrated circuits, including the process used for its TMF8701 product, infringe patents related to efficiently implementing design changes and managing interlayer capacitance in semiconductor manufacturing.
- Technical Context: The technology concerns electronic design automation (EDA) software and methods used to create complex semiconductor chips, focusing on process optimizations that accelerate design cycles and improve final device performance.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or specific prosecution history events related to the patents-in-suit. It does state that the patents are part of a larger portfolio originating from Bell Labs and its successors.
Case Timeline
| Date | Event |
|---|---|
| 2004-11-17 | Priority Date for U.S. Patent No. 7,396,760 |
| 2004-12-17 | Priority Date for U.S. Patent No. 7,231,626 |
| 2007-06-12 | U.S. Patent No. 7,231,626 Issued |
| 2008-07-08 | U.S. Patent No. 7,396,760 Issued |
| 2023-01-25 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - "Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows"
- Patent Identification: U.S. Patent No. 7,231,626, "Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows," issued June 12, 2007 (’626 Patent). (Compl. ¶26).
The Invention Explained
- Problem Addressed: The patent’s background describes that prior methods for implementing an engineering change order (ECO) in an integrated circuit (IC) design were highly inefficient. Design tools had to be run for the entire circuit design, even if the change was very small, resulting in a "typical turnaround time" of "about one week" (’626 Patent, col. 2:15-19, 37-44).
- The Patented Solution: The invention solves this problem by creating a "window" that isolates only the portion of the IC design affected by the ECO. Instead of re-processing the entire circuit, computationally intensive tasks like routing are performed only on the nets within this smaller, bounded window. The results from this incremental process are then merged back into the full design, which "substantially reduces the run time of the routing tools." (’626 Patent, Abstract; Compl. ¶¶33-34).
- Technical Importance: This method of localized, incremental processing makes implementing late-stage design fixes faster and less resource-intensive, a significant advantage in the competitive semiconductor industry where time-to-market is paramount (Compl. ¶35).
Key Claims at a Glance
- The complaint asserts infringement of Claim 1, an independent method claim (Compl. ¶37).
- The essential elements of Claim 1 include:
- Receiving an IC design and an ECO as inputs.
- Creating at least one "window" that encloses the change and defines an area "less than an entire area of the integrated circuit design."
- Performing "incremental routing" only for nets enclosed by the window.
- Replacing the area in a copy of the design with the results of the incremental routing to create a revised design.
- Generating the revised IC design as output.
- The complaint alleges infringement of "one or more claims," reserving the right to assert additional claims, including dependent claims (Compl. ¶60).
U.S. Patent No. 7,396,760 - "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits"
- Patent Identification: U.S. Patent No. 7,396,760, "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits," issued July 8, 2008 (’760 Patent). (Compl. ¶40).
The Invention Explained
- Problem Addressed: During semiconductor manufacturing, "dummy fill" material is added to sparse areas of a layer to ensure surface planarity for subsequent processing steps like Chemical Mechanical Planarization (CMP). The patent states that conventional methods considered dummy fill placement only within a single layer, ignoring the effects between layers. This could result in dummy features on adjacent layers overlapping, creating unwanted "interlayer bulk capacitance" that slows down signals and degrades circuit performance. (’760 Patent, col. 1:66-2:6; Compl. ¶8).
- The Patented Solution: The patented method addresses this by treating successive layers as a pair. It analyzes the potential overlap of dummy fill between the two layers and then "re-arrang[es]" the dummy fill features on one or both layers to minimize this overlap. The patent suggests this can be done by placing features in an offset or "checkerboard pattern." (’760 Patent, Abstract; col. 2:7-13; Compl. ¶10).
- Technical Importance: By intelligently placing dummy fill to account for interlayer effects, the invention allows manufacturers to achieve necessary surface planarity while simultaneously improving the electrical performance and speed of the IC (Compl. ¶11).
Key Claims at a Glance
- The complaint asserts infringement of Claim 1, an independent method claim (Compl. ¶47).
- The essential elements of Claim 1 include:
- Obtaining layout information for an IC with a plurality of layers.
- Obtaining a first and second "dummy fill space" for two successive layers.
- Determining an "overlap" between the two spaces.
- "Minimizing the overlap" by rearranging the dummy fill features.
- The complaint alleges infringement of "one or more claims," reserving the right to assert additional claims (Compl. ¶72).
III. The Accused Instrumentality
Product Identification
- The complaint names Defendant's TMF8701 semiconductor device as an exemplary "OSRAM Accused Product" (Compl. ¶1). The infringement allegations are directed more broadly at the "Accused Processes" that OSRAM allegedly uses to design its semiconductor devices (Compl. ¶¶55, 68).
Functionality and Market Context
- The complaint alleges that OSRAM's "Accused Processes" employ a variety of third-party EDA design tools, such as those from Cadence, Synopsys, and/or Siemens (Compl. ¶¶55, 68).
- These processes are alleged to perform "incremental routing" to implement ECOs, thereby generating revised IC designs (Compl. ¶55).
- The processes are also alleged to "rearrange dummy fill to minimize its overlap in successive layers" in a "timing aware fashion" to reduce interlayer capacitance (Compl. ¶68). The complaint does not provide further details on the market positioning of the TMF8701.
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | OSRAM's Accused Processes begin with an integrated circuit design that requires modification. | ¶55 | col. 6:58-59 |
| (b) receiving as input an engineering change order to the integrated circuit design; | The Accused Processes are used for "implementing an ECO." | ¶55 | col. 6:60-61 |
| (c) creating at least one window in the integrated circuit design that encloses a change...wherein the window is bounded by coordinates that define an area that is less than an entire area... | The Accused Processes route only the "nets affected by the ECO" and merge "that changed area," which implies the use of a bounded, localized area for processing. | ¶55 | col. 6:62-67 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | OSRAM allegedly "employs a design tool...to perform incremental routing" by "only routing the nets affected by the ECO." | ¶55 | col. 7:12-16 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; | The process involves "merging that changed area into the overall circuit layout as required by claim 1." | ¶55 | col. 7:1-5 |
| (f) generating as output the revised integrated circuit design. | The purpose of the process is "to generate a revised integrated circuit design." | ¶55 | col. 7:6-7 |
- Identified Points of Contention:
- Scope Questions: The complaint alleges OSRAM "employs" third-party design tools to perform the claimed method. A central question may be whether OSRAM’s use and configuration of these general-purpose tools meets the claim limitation of "performing" the specific, ordered steps of the patented method.
- Technical Questions: What evidence demonstrates that the accused process "creat[es] at least one window" for the incremental routing step itself? While the complaint alleges windowing for related, dependent claim features like parasitic extraction and design rule checks (Compl. ¶¶56-57), the evidence linking the "window" concept directly to the independent claim's core "incremental routing" step will be critical.
’760 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| obtaining layout information of the integrated circuit, the integrated circuit including a plurality of layers; | The Accused Processes inherently use layout information of successive layers to place dummy fill. | ¶68 | col. 6:10-12 |
| obtaining a first dummy fill space for a first layer...and a second dummy fill space for a second layer...; | The processes identify areas for dummy fill on successive layers. | ¶68 | col. 6:13-18 |
| determining an overlap between the first dummy fill space and the second dummy fill space; and | The complaint alleges the process minimizes capacitance "after determining their overlap as required by claim 1." | ¶68 | col. 6:19-21 |
| minimizing the overlap by re-arranging a plurality of first dummy fill features and a plurality of second dummy fill features... | OSRAM allegedly uses design tools "to rearrange dummy fill to minimize its overlap in successive layers," including the ability to "stagger the dummy fill." | ¶68 | col. 6:22-25 |
- Identified Points of Contention:
- Scope Questions: The claim requires "minimizing the overlap." The construction of this term will be a focal point. Does it require an active, targeted optimization to achieve the lowest possible overlap, or is any process that results in a reduction of overlap sufficient to meet the limitation?
- Technical Questions: What is the evidence that the accused process rearranges dummy fill for the specific purpose of reducing interlayer overlap, as the patent teaches? A defendant may argue that any observed reduction is an incidental byproduct of rearranging fill to optimize for other factors, such as intralayer timing or local density gradients, which are not the primary focus of the patented invention.
V. Key Claim Terms for Construction
’626 Patent
- The Term: "window"
- Context and Importance: This term is the core concept of the ’626 patent. Its definition will determine whether the accused method of isolating "nets affected by the ECO" for localized processing constitutes infringement. Practitioners may focus on this term because it delineates the boundary between the prior art (re-processing the entire design) and the invention.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification provides a definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 4:59-62). This could support an argument that any method of logically or physically isolating a sub-region for processing meets the definition.
- Evidence for a Narrower Interpretation: Figure 4 depicts a window (404) as a distinct box bounded by specific coordinates (X1, Y1):(X2, Y2) (’626 Patent, Fig. 4). This could support a narrower construction requiring a formally defined, coordinate-based bounding box structure, rather than just a logical grouping of circuit elements.
’760 Patent
- The Term: "minimizing the overlap"
- Context and Importance: This term describes the key functional step of the method claim. Its construction will be critical in determining whether the accused process performs the inventive work. Practitioners may focus on this term because its ambiguity—whether it implies a process or a final state—creates a clear point of dispute.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification repeatedly uses phrases like "reduce inter-layer capacitance" (’760 Patent, col. 2:8-10), which could support a construction where "minimizing" refers to the act of undertaking a process intended to reduce overlap, without requiring a perfect or mathematically optimal result.
- Evidence for a Narrower Interpretation: The abstract states the invention may "eliminate large overlap area," and the goal is to "minimize dummy filling overlaps" (’760 Patent, Abstract). This language could support a narrower construction requiring the accused process to achieve a state of very low, or near-zero, overlap, not just any amount of reduction.
VI. Other Allegations
- Indirect Infringement: The complaint does not plead specific facts to support claims for indirect infringement (inducement or contributory infringement). The allegations are centered on direct infringement under 35 U.S.C. § 271(a).
- Willful Infringement: The complaint does not use the term "willful." It does allege that the infringement is "exceptional" and requests attorneys' fees under 35 U.S.C. § 285 (Compl. ¶¶61, 73). However, it does not plead specific facts typically used to support willfulness, such as pre-suit knowledge of the patents or egregious conduct.
VII. Analyst’s Conclusion: Key Questions for the Case
- A primary issue for both patents will be one of evidence and attribution: can the plaintiff produce evidence from discovery to show that the defendant’s internal, proprietary design flows, which utilize third-party EDA tools, are in fact configured and used to perform the specific, ordered steps recited in the method claims?
- For the ’626 patent, a central question will be one of definitional scope: can the term "window," which is described in the patent with specific geometric properties, be construed to read on the accused process of logically isolating "affected nets" for incremental processing?
- For the ’760 patent, the dispute may turn on a question of functional intent and degree: does the accused process "minimize" interlayer overlap as an intentional design goal, as taught by the patent, or is any reduction in overlap merely an incidental side effect of optimizing for other manufacturing or performance constraints?