Bell Semiconductor LLC v. Cisco Systems Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Bell Semiconductor, LLC (Delaware)
  • Defendant: Cisco Systems, Inc. (Delaware)
  • Plaintiff’s Counsel: Devlin Law Firm LLC
• Case Identification: 4:24-cv-00937, E.D. Tex., 10/18/2024
• Venue Allegations: Plaintiff alleges venue is proper because Cisco has committed acts of infringement and maintains regular and established places of business in the district, including facilities in Allen and Richardson, Texas. The complaint includes a screenshot of a Cisco job posting for a "Switching Escalation Engineer" in Richardson, Texas, to support its allegation of a local business presence.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor packages and the products containing them, such as certain virtual interface cards, infringe patents related to semiconductor package design for thermal reliability and high-speed signal isolation.
• Technical Context: The patents address challenges in modern semiconductor packaging, specifically managing physical stress from heat and electrical noise from high-speed circuits in densely packed integrated circuits.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement of the ’245 patent on June 30, 2023, and of both asserted patents on October 17, 2024. Public records attached to the patent documents indicate that on February 18, 2024, the assignee filed a disclaimer for claims 7 and 9-12 of the ’245 patent, which are not asserted in this action.

Case Timeline

Date	Event
2003-10-08	U.S. Patent No. 7,345,245 Priority Date
2006-04-06	U.S. Patent No. 7,646,091 Priority Date
2008-03-18	U.S. Patent No. 7,345,245 Issued
2010-01-12	U.S. Patent No. 7,646,091 Issued
2023-06-30	Alleged notice to Cisco of ’245 Patent infringement
2024-02-18	Disclaimer filed for claims 7 and 9-12 of ’245 Patent
2024-10-17	Alleged notice to Cisco of infringement by Accused Products
2024-10-18	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,345,245 - "Robust High Density Substrate Design for Thermal Cycling Reliability," issued March 18, 2008

The Invention Explained

• Problem Addressed: In high-density semiconductor packages (specifically, organic BGA substrates), thermal cycling causes physical stress. This stress is concentrated at the corners of the die, which can lead to cracks initiating at the edges of ball pads and propagating into the signal trace layers above, causing device failure (Compl. ¶15; ’245 Patent, col. 1:19-22, col. 2:1-3).
• The Patented Solution: The invention proposes a design rule to improve reliability by creating a keep-out zone for signal traces in the high-stress areas. It teaches routing signal traces away from the ball pads located directly under the corner of the die, specifically within an area defined as "two ball pad pitches" from the die corner, thereby preventing cracks from affecting the electrical pathways (Compl. ¶16; ’245 Patent, Abstract; col. 3:40-54). Figure 5 illustrates a routing layer where signal traces (64) are routed to avoid the high-stress area (58) associated with the die corner (54a) (’245 Patent, Fig. 5).
• Technical Importance: This design methodology aimed to enhance the structural integrity and long-term reliability of densely packed semiconductor packages without sacrificing significant signal routing density, a critical trade-off in package design (’245 Patent, col. 2:15-22).

Key Claims at a Glance

• The complaint asserts infringement of at least independent Claim 1 (Compl. ¶17).
• Claim 1 Elements:
  • A semi-conductor package comprising:
  • a top layer having a die mounted thereon, said die having a corner; and
  • a plurality of layers under the top layer, said plurality of layers comprising a bottom routing layer having signal traces thereon, and a ball pad layer under the bottom routing layer, said ball pad layer having a plurality of ball pads,
  • wherein none of the signal traces of the bottom routing layer are located over ball pads of the ball pad layer which are disposed in an area within two ball pad pitches of the corner of the die.

U.S. Patent No. 7,646,091 - "Semiconductor Package and Method Using Isolated Vss Plane to Accommodate High Speed Circuitry Ground Isolation," issued January 12, 2010

The Invention Explained

• Problem Addressed: In modern integrated circuits that combine high-speed and low-speed circuitry, using a single shared ground plane causes problems. Electrical noise and "ground bounce" from the high-speed circuits can interfere with the operation of the sensitive low-speed circuits (Compl. ¶23; ’091 Patent, col. 2:10-14).
• The Patented Solution: The patent teaches the use of two separate, electrically isolated ground planes within the same semiconductor package. One ground plane is dedicated to the high-speed circuitry, and the other is dedicated to the low-speed circuitry, preventing noise from coupling between them (Compl. ¶24; ’091 Patent, Abstract). The specification describes this architecture with a first ground plane (e.g., 204) for low-speed circuitry and a second, isolated ground plane (e.g., 205) for high-speed circuitry (’091 Patent, col. 4:25-32, Fig. 2).
• Technical Importance: This approach enabled the integration of mixed-signal (high- and low-speed) systems into a single package while maintaining signal integrity, which is crucial for high-performance computing and communication devices (’091 Patent, col. 2:35-39).

Key Claims at a Glance

• The complaint asserts infringement of at least independent Claim 1 (Compl. ¶25).
• Claim 1 Elements:
  • A semiconductor integrated circuit (IC) package which comprises:
  • a substrate having a first surface and a second surface;
  • a first layer of the substrate includes a first ground plane (for low speed circuitry) and a second ground plane (for high speed circuitry) that is spatially separated and electrically isolated from the first;
  • a second layer of the substrate includes a third ground plane (for low speed circuitry) and a fourth ground plane (for high speed circuitry) that is spatially separated and electrically isolated from the third;
  • a plurality of electrical connections connecting the first ground plane with solder balls;
  • a plurality of additional electrical connections connecting the second ground plane with solder balls;
  • peripheral electrical contacts for connection with external circuitry; and
  • at least one reference plane associated with each layer of the substrate and the ground planes.

III. The Accused Instrumentality

Product Identification

• The complaint identifies the "Accused Products" as the "Cisco 08-1072-03 semiconductor integrated circuit package" and products containing it, such as the "Cisco UCS Virtual Interface Card 1457 system board" (Compl. ¶1, ¶30).

Functionality and Market Context

• The complaint does not provide specific technical details on the functionality or operation of the accused package or board. It alleges these components are semiconductor devices used in Cisco's products (Compl. ¶1). The complaint includes a screenshot of a job posting for a "Switching Escalation Engineer" to work with the "Enterprise Switching Engineering Group," suggesting the accused technologies may be used in Cisco's enterprise networking products (Compl. pp. 5-6).

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits detailing its infringement theories (Compl. ¶31, ¶41). The narrative allegations are summarized below.

• ’245 Patent Infringement Allegations
  The complaint alleges that the Cisco 08-1072-03 package and products containing it infringe one or more claims of the ’245 patent (Compl. ¶30). The implicit theory is that the accused package is a multi-layer semiconductor package that has a structure corresponding to the elements of Claim 1, yet fails to follow the patent's proscriptive step of keeping signal traces out of the high-stress region near the die corner. The analysis will depend on a physical inspection of the accused package to determine the layout of its die, ball pads, and signal traces.

• ’091 Patent Infringement Allegations
  The complaint alleges that the same accused products infringe one or more claims of the ’091 patent (Compl. ¶40). The infringement theory is that the accused package utilizes a multi-layer substrate with separate, electrically isolated ground planes for high-speed and low-speed circuitry, as claimed. This analysis will require reverse engineering the package to map its internal layers, ground plane structures, and electrical connections.

• Identified Points of Contention:

  • Scope Questions (’245 Patent): A central question will be the construction of the phrase "an area within two ball pad pitches of the corner of the die." The case may turn on how a "ball pad pitch" is measured and how the resulting two-dimensional "area" is defined and applied to the layout of the accused device.
  • Technical Questions (’091 Patent): A key factual question is whether the ground planes in the accused package are genuinely "electrically isolated" as required by the claim, or if they share common connections that would defeat the claim limitation. Furthermore, the distinction between "low speed" and "high speed" circuitry within the accused device may become a point of dispute.

V. Key Claim Terms for Construction

For the ’245 Patent:

• The Term: "an area within two ball pad pitches of the corner of the die"
• Context and Importance: This phrase defines the specific geometric "keep-out" zone that is the central feature of the invention. Infringement hinges entirely on whether the accused product has signal traces over ball pads inside this defined area. Practitioners may focus on this term because its precise definition is critical and potentially ambiguous without a clear construction.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not appear to provide language suggesting a broad interpretation beyond its plain meaning. A party might argue the term should be given its plain and ordinary meaning to one of skill in the art of package design at the time.
  • Evidence for a Narrower Interpretation: The specification states, "The high stress zone 58 extends approximately two ball pitches away from the die corner 54a in each direction" (’245 Patent, col. 3:23-26). This, along with the depiction in Figure 4, suggests a specific, bounded rectangular or square-like area extending from the corner, which could be argued as a limiting definition.

For the ’091 Patent:

• The Term: "spatially separated and electrically isolated"
• Context and Importance: This term is the core of the claimed solution to the signal integrity problem. The entire purpose of the patent is to separate the grounds. Whether the accused device meets this limitation is a dispositive issue for infringement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue that any degree of separation that achieves the patent's stated goal of reducing noise and ground bounce meets the limitation, even if minor, high-impedance connections exist.
  • Evidence for a Narrower Interpretation: The patent repeatedly emphasizes the separation, describing the invention as using "separate electrically isolated ground planes" (’091 Patent, col. 4:25-26) and showing them as physically distinct structures in diagrams like Figure 2 (planes 204 and 205) and Figure 6 (planes 611 and 631). A party could argue this requires complete electrical isolation with no shared conductive paths.

VI. Other Allegations

Willful Infringement

• The complaint alleges willful infringement for both patents. For the ’245 patent, willfulness is alleged based on actual notice provided on or about June 30, 2023, and again on October 17, 2024 (Compl. ¶33). For the ’091 patent, willfulness is alleged based on actual notice provided on or about October 17, 2024 (Compl. ¶43). Plaintiff claims this alleged knowledge makes ongoing infringement willful and deliberate.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case appears to hinge on two primary questions, one geometric and one electrical:

1. A core issue will be one of definitional scope: For the ’245 patent, can the phrase "an area within two ball pad pitches of the corner of the die" be construed with sufficient clarity to determine whether the accused package’s signal traces fall within this prohibited zone? The outcome will likely depend on expert testimony regarding the physical layout of the accused device.

2. A key evidentiary question will be one of technical implementation: For the ’091 patent, does the accused package contain ground planes that are "electrically isolated" in the manner required by the claims? This will require a detailed technical analysis of the package's internal structure to determine if the high-speed and low-speed grounds are truly separate or if they are interconnected in a way that falls outside the claim scope.