DCT

4:25-cv-01424

Near Field Electronics LLC v. Aritzia Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 4:25-cv-01424, E.D. Tex., 12/19/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendants conduct business through a regular and established place of business in Plano, Texas, and have committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that credit card reader devices used by Defendant, which incorporate a specific NXP Near Field Communication (NFC) chip, infringe five patents related to semiconductor interface protocols, configurable bus architectures, and power management.
  • Technical Context: The patents-in-suit relate to foundational integrated circuit technologies for managing communication between devices, adapting to different bus standards (like USB), and controlling power consumption, which are critical functions in modern electronics, including point-of-sale payment systems.
  • Key Procedural History: The complaint asserts infringement of five patents, four of which expired between 2021 and 2023. For these expired patents, Plaintiff asserts liability only for a past damages period, beginning December 19, 2019 (six years prior to the complaint filing) and ending on each patent’s respective expiration date. Infringement of the fifth patent is alleged to be ongoing.

Case Timeline

Date Event
2000-06-21 ’201 Patent Priority Date
2000-07-25 ’071 Patent Priority Date
2000-08-28 ’727 Patent Priority Date
2002-06-28 ’350 Patent Priority Date
2004-02-10 ’201 Patent Issue Date
2004-05-25 ’071 Patent Issue Date
2005-01-11 ’531 Patent Priority Date
2005-10-25 ’350 Patent Issue Date
2006-02-07 ’727 Patent Issue Date
2008-05-13 ’531 Patent Issue Date
2019-12-19 Alleged infringement liability period begins
2021-11-21 ’071 Patent Expiration Date
2022-01-31 ’201 Patent Expiration Date
2022-04-14 ’727 Patent Expiration Date
2023-08-12 ’350 Patent Expiration Date
2025-12-19 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,691,201 - "Dual Mode USB-PS/2 Device"

The Invention Explained

  • Problem Addressed: The patent describes that peripheral devices supporting multiple communication protocols, such as both the Universal Serial Bus (USB) and the older PS/2 standard, conventionally required additional external components, dedicated I/O pins, and complex firmware, which increased cost and compromised performance (Compl. ¶12; ’201 Patent, col. 1:28-50).
  • The Patented Solution: The invention provides a single integrated circuit that can automatically detect which protocol a connected bus is using (e.g., USB or PS/2) and configure itself to operate in the correct mode using a single, shared set of I/O pins, thereby eliminating the need for redundant external hardware (’201 Patent, Abstract; col. 2:51-54). The core concept is illustrated in the block diagram of Figure 1, which shows a unified "USB - PS/2 DRIVER" handling signals for both protocols.
  • Technical Importance: This single-chip solution simplified peripheral design, reduced board space, and lowered costs for devices like computer mice that needed to maintain compatibility with both legacy (PS/2) and then-emerging (USB) interface standards (Compl. ¶13; ’201 Patent, col. 1:50-2:8).

Key Claims at a Glance

  • The complaint asserts independent method claim 14 (Compl. ¶32).
  • Claim 14 requires a method for automatically selecting a signaling protocol, comprising the steps of:
    • (A) detecting a signaling protocol of a bus connected to an integrated circuit that operates in a plurality of signaling protocols; and
    • (B) configuring said integrated circuit to communicate in one of said plurality of signaling protocols in response to said detected signaling protocol, wherein each of said selected protocols operate over said connected bus through a single set of pins.
  • The complaint reserves the right to assert additional claims (Compl. ¶33).

U.S. Patent No. 6,742,071 - "Real-time I/O Processor Used to Implement Bus Interface Protocols"

The Invention Explained

  • Problem Addressed: The patent explains that conventional approaches for implementing bus interfaces were often rigid and protocol-specific, limiting flexibility and market relevance as standards evolved. User-programmable interfaces were also limited, often relying on a fixed number of wait-states that could not handle complex signaling (Compl. ¶17; ’071 Patent, col. 1:16-48).
  • The Patented Solution: The invention discloses a programmable, real-time I/O processor, referred to as a General-Purpose Interface (GPIF), that can act as a master device to control external logic. This processor uses a limited instruction set to generate complex, interface-specific waveforms and respond to external events on a clock-cycle-by-clock-cycle basis, replacing inflexible, hard-wired logic with a programmable solution (’071 Patent, Abstract; col. 4:66-5:11). Figure 6 illustrates this architecture, showing a finite state machine and lookup table generating control outputs.
  • Technical Importance: This programmable architecture provided a flexible and high-speed solution for interfacing with multiple or evolving bus protocols, allowing a single chip design to support various standards without requiring new hardware (Compl. ¶17; ’071 Patent, col. 6:4-16).

Key Claims at a Glance

  • The complaint asserts independent method claim 15 (Compl. ¶37).
  • Claim 15 requires a method for providing an interface to an external bus, comprising the steps of:
    • (A) generating a plurality of first control signals in response to a current state of a processor;
    • (B) progressing to a next state based on the current state, an internal control signal, and an input signal from the external bus;
    • (C) driving at least one output control signal onto the external bus; and
    • (D) updating the current state to the next state.
  • The complaint reserves the right to assert additional claims (Compl. ¶38).

U.S. Patent No. 6,959,350 - "Configurable USB Interface With Virtual Register Architecture"

  • Technology Synopsis: The patent addresses the inflexibility of conventional USB interface controllers with hard-coded endpoint configurations, which required writing and maintaining separate HDL code for each version (Compl. ¶21). The invention is a configurable bus interface controller that uses an HDL-based configuration package to generate the necessary circuitry, allowing the controller to be flexibly configured for different endpoint arrangements without new HDL code (Compl. ¶¶ 20, 22).
  • Asserted Claims: Independent claim 10 (Compl. ¶42).
  • Accused Features: The NXP PN512 NFC Front-End and similar components in Defendants' credit card readers (Compl. ¶42).

U.S. Patent No. 6,996,727 - "Power Supply for Universal Serial Bus Interface with Programmable Bus Pullup Resistor"

  • Technology Synopsis: The patent addresses the problem of power consumption in USB interfaces that, at the time, provided a constant voltage supply with no low-power mode (Compl. ¶26). The patented solution is a power supply architecture for a bus interface that operates in two modes: a standard mode and a power-down standby mode that uses a low-power programmable resistor to maintain the necessary pullup function, thereby minimizing power usage during idle states (Compl. ¶25).
  • Asserted Claims: Independent claim 18 (Compl. ¶47).
  • Accused Features: The NXP PN512 NFC Front-End and similar components in Defendants' credit card readers (Compl. ¶47).

U.S. Patent No. 7,373,531 - "Signal Detection Method... and Electronic Apparatus"

  • Technology Synopsis: The patent is directed to methods for detecting signals and power status in an electronic device to reduce power consumption (Compl. ¶¶ 29-30). The solution involves applying a signal to the gates of connected transistors and detecting the presence, absence, or state of the signal based on whether a "through current" flows in the circuit, enabling the device to enter a power-saving state when a target is not operational (Compl. ¶29).
  • Asserted Claims: Independent claim 2 (Compl. ¶52).
  • Accused Features: The NXP PN512 NFC Front-End and similar components in Defendants' credit card readers (Compl. ¶52).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the accused instrumentalities as "credit card reader device equipped with an NXP PN512 NFC Front-End" and any other NFC-capable readers with similar functionality (Compl. ¶¶ 32, 37, 42, 47, 52).

Functionality and Market Context

  • The complaint alleges that Defendants use the accused credit card readers in the "regular course of their business operations for processing NFC payment transactions" (Compl. ¶¶ 34, 39). The core accused functionality is enabling contactless payments via Near Field Communication. The complaint alleges these products are sold and used throughout the United States (Compl. ¶¶ 3, 4).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that the Accused Instrumentalities directly infringe the asserted patents when used for their intended purpose of processing NFC payments (Compl. ¶¶ 34, 39). The complaint references exemplary infringement analyses in exhibits (e.g., Exhibit A-1, B-1), but these exhibits were not provided with the complaint document (Compl. ¶¶ 33, 38). The complaint does not contain narrative infringement theories or claim charts in its body.

  • Identified Points of Contention:
    • ’201 Patent (Scope Questions): The ’201 Patent is titled "Dual Mode USB-PS/2 Device" and its claims and specification are directed to automatically selecting between those two specific protocols. The Accused Instrumentality is an NFC reader, which operates on different protocols (e.g., ISO/IEC 14443). A central dispute may be whether the claimed method of selecting between USB and PS/2 protocols can be construed to read on the protocol-handling functions of an NFC reader.
    • ’071 Patent (Technical Questions): The ’071 Patent claims a method of providing an interface by "executing an instruction" from a "plurality of states" to generate control signals. This suggests a specific programmable, processor-like architecture. The complaint does not provide technical details on the architecture of the accused NXP PN512 chip. A key technical question will be whether the NXP chip's operation can be fairly characterized as executing instructions in this manner, or if it employs a different, non-infringing architecture such as hard-coded logic.

V. Key Claim Terms for Construction

For the ’201 Patent

  • The Term: "a plurality of signaling protocols" (Claim 14) / "a Universal Serial Bus (USB) protocol and a PS/2 protocol" (Claim 15, dependent on 14).
  • Context and Importance: The applicability of this patent to an NFC reader hinges on the scope of these terms. Practitioners may focus on whether "plurality of signaling protocols" is limited by the patent's explicit and repeated focus on USB and PS/2, or if it can be interpreted more broadly to encompass other protocol-switching technologies.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Claim 1 is directed more generally to an "integrated circuit configured to operate in a plurality of signaling protocols," which could suggest the invention is not conceptually limited to just two specific examples (’201 Patent, col. 5:16-17).
    • Evidence for a Narrower Interpretation: The patent's title, abstract, background, and detailed embodiments exclusively discuss the USB and PS/2 protocols (’201 Patent, Title; Abstract; col. 1:17-27). This extensive focus may be used to argue that the invention's scope is confined to the specific protocols disclosed.

For the ’071 Patent

  • The Term: "executing an instruction defining a plurality of first control signals" (Claim 15).
  • Context and Importance: This term appears central to defining the invention as a programmable, instruction-driven I/O processor. The infringement analysis will likely turn on whether the accused NXP chip's operations constitute "executing an instruction" as understood in the context of the patent, or if it operates via a different mechanism.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes the invention as a "generic interface" capable of implementing "multiple industry-standard protocols" and "customer-specific interfaces," which could support an argument that the term should not be limited to a rigid definition of a traditional CPU instruction set (’071 Patent, col. 2:38-41; col. 6:55-58).
    • Evidence for a Narrower Interpretation: The specification discloses a specific, limited instruction set comprising a "branch on signal" instruction and a "wait N clocks" instruction, and provides detailed examples of their format and use (’071 Patent, Fig. 11a-11d; col. 7:14-23). This may support a narrower construction limited to architectures that operate based on a stored program of such commands.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for the ’531 Patent. The allegations are based on Defendants having knowledge of the patent "since at least the time each Defendant received notice" (i.e., from the complaint) and inducing infringement by "advertising and distributing the Accused Instrumentalities and providing instruction materials" (Compl. ¶¶ 56-57).
  • Willful Infringement: Willfulness is alleged for the ’531 Patent based on post-suit knowledge, stating that "Since the filing of this Complaint, each Defendant’s infringement has been willful" (Compl. ¶58).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Definitional Scope: A core issue will be whether the claims of patents rooted in specific computer peripheral technologies—such as auto-selecting between USB and PS/2 (’201 Patent) or configurable USB endpoints (’350 Patent)—can be construed to cover the distinct hardware architecture and communication protocols of a modern NFC payment reader.
  2. Architectural Equivalence: An evidentiary question will be one of technical operation: does the accused NXP chip's internal architecture function in a manner equivalent to the specific programmable, instruction-based I/O processor claimed in the ’071 Patent, or the dual-mode power supply of the ’727 Patent? The complaint's conclusory allegations will require substantial technical discovery to substantiate this architectural mapping.
  3. Damages for Expired Patents: As four of the five asserted patents have expired, the case will likely involve a significant focus on calculating reasonable royalty damages for a closed historical period, rather than future-looking remedies like an injunction or ongoing royalties for those patents.