DCT

6:09-cv-00542

Nazomi Communications Inc v. Nokia Corp

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Key Events
Complaint

I. Executive Summary and Procedural Information

Case Timeline

Date Event
1998-12-08 Priority Date for ’362 and ’436 Patents
2006-07-18 U.S. Patent No. 7,080,362 Issues
2007-05-29 U.S. Patent No. 7,225,436 Issues
2009-12-07 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,080,362: "Java virtual machine hardware for RISC and CISC processors" (Issued July 18, 2006)

The Invention Explained

  • Problem Addressed: The patent describes the slow execution speed of Java programs on processors for which they were not natively compiled (Compl. ¶18; ’362 Patent, col. 1:47-55). Software-based Java Virtual Machines (JVMs), which translate universal "bytecode" into native processor instructions, create a performance bottleneck, particularly for low-cost, low-power consumer appliances that lack powerful processors (’362 Patent, col. 1:56-67).
  • The Patented Solution: The invention proposes implementing parts of the JVM in dedicated hardware, described as a "Java™ hardware accelerator" (’362 Patent, Abstract). This hardware unit works in conjunction with a standard CPU to directly translate Java bytecodes into native instructions, thereby bypassing the software bottleneck and speeding up program execution (’362 Patent, col. 2:8-14; Fig. 1).
  • Technical Importance: This approach sought to make the versatile, platform-independent Java language practical for the burgeoning market of embedded systems and consumer electronics, where performance and power efficiency were critical constraints (’362 Patent, col. 1:56-67).

Key Claims at a Glance

  • The complaint does not specify which claims are asserted. Independent claim 1 is a representative method claim.
  • Independent Claim 1: A method for a CPU capable of processing both stack-based (e.g., Java) and register-based (e.g., native) instructions, comprising the steps of:
    • Maintaining an operand stack for stack-based instructions within a register file.
    • Moving operands between this register file and memory using an overflow/underflow mechanism.
    • Maintaining an indication of the operand stack's depth.
    • Processing both register-based and stack-based instructions in the CPU's execution unit.
    • Generating exceptions for certain pre-selected stack-based instructions.
  • The complaint reserves the right to assert other claims, including dependent claims.

U.S. Patent No. 7,225,436: "Java hardware accelerator using microcode engine" (Issued May 29, 2007)

The Invention Explained

  • Problem Addressed: Like its parent, the ’436 Patent addresses the need for efficient execution of Java bytecodes on embedded systems (’436 Patent, col. 1:42-55). It builds on the hardware acceleration concept to provide a more flexible and powerful architecture.
  • The Patented Solution: The invention discloses a hardware accelerator architecture featuring a separate "decode stage" and "microcode stage" (’436 Patent, Abstract; col. 2:49-59). This separation allows the decode stage to process multiple simple Java bytecodes in parallel (instruction-level parallelism), while the microcode stage enables the conversion of a single complex bytecode into a sequence of multiple native instructions. This design aims to provide a versatile hardware solution adaptable to various CPU types (’436 Patent, col. 8:25-33).
  • Technical Importance: This architecture provided a more sophisticated method for hardware acceleration, potentially yielding greater performance gains and adaptability for processor designers seeking to support Java efficiently (’436 Patent, col. 2:45-59).

Key Claims at a Glance

  • The complaint does not specify which claims are asserted. Independent claim 5 is a representative apparatus claim.
  • Independent Claim 5: A CPU comprising:
    • Execution logic for processing register-based instructions.
    • A hardware accelerator for processing stack-based instructions.
    • An operand stack for the stack-based instructions, maintained in a register file as a "ring buffer."
    • An overflow/underflow mechanism for moving operands between the register file and memory.
    • A "bytecode buffer" to receive stack-based instructions.
    • An "instruction decode unit" coupled to the bytecode buffer.
    • A common program counter for both instruction types.
  • The complaint reserves the right to assert other claims, including dependent claims.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are a range of consumer electronics, including the Nokia 770 internet tablet, Microsoft Zune music player, Amazon Kindle 2 eReader, Western Digital My Book World Edition storage device, Garmin Nuvi 205 navigation device, Sling Media Slingbox Pro-HD video recorder, VIZIO L37 and VL320M televisions, and the Iomega Home Media Network Hard Drive (Compl. ¶¶ 23-30).

Functionality and Market Context

  • The complaint’s central technical allegation is that each accused product "incorporates" a specific processor core (e.g., ARM926TEJ, ARM1136JF-S, ARM926EJ-S) that is "capable of Java hardware acceleration" (Compl. ¶¶ 23-30). The infringement theory rests on this alleged capability.
  • The complaint asserts that Java is a widely adopted platform used on "hundreds of millions of devices," positioning the accused products within a significant market for Java-enabled electronics (Compl. ¶18).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not provide an element-by-element mapping of the accused products to the patent claims. The infringement theory is based on the general allegation that the identified ARM processor cores are "capable of Java hardware acceleration" (Compl. ¶22). The following charts summarize how these general allegations might map to the elements of representative independent claims.

’362 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for processing instructions in a central processing unit (CPU) capable of executing instructions of a plurality of instruction sets, including a stack-based and a register-based instruction set... The accused ARM processor cores are alleged to be capable of Java hardware acceleration, which entails processing both native (register-based) and Java (stack-based) instructions. ¶¶22-30 col. 1:9-20
maintaining data for register-based instructions ... and an operand stack for operands associated with stack-based instructions ... in a first register file... The accused processors allegedly implement a hardware-accelerated JVM, which requires maintaining an operand stack for Java bytecodes in the processor’s register file. ¶¶22-30 col. 4:41-52
...wherein at least some of the operands are moved between the register file and memory via at least one of an overflow and underflow mechanism; The functionality of the accused processors allegedly includes managing the operand stack, which implies a mechanism to handle overflow and underflow between the register file and main memory. ¶¶22-30 col. 4:60-67
maintaining an indication of a depth of the operand stack; The alleged hardware acceleration capability implies a mechanism to track the depth of the operand stack to manage push and pop operations correctly. ¶¶22-30 col. 5:40-45
processing the stack-based instructions including generating a second output, and processing the second output in the execution unit... The accused processors allegedly translate Java bytecodes (stack-based instructions) into native instructions (the second output) for execution. ¶¶22-30 col. 4:5-11

Identified Points of Contention

  • Technical Question: The complaint provides no evidence that the accused ARM processors actually perform the specific method of Claim 1. A central question is whether the "Java hardware acceleration" they are "capable of" involves maintaining an operand stack in a register file with an overflow/underflow mechanism, as claimed, or if they use a different technical approach.
  • Scope Question: How the court defines "operand stack ... in a first register file" will be critical. The dispute may turn on whether the way the accused ARM cores manage stack data qualifies under the patent's definition, or if it is technically distinct.

’436 Patent Infringement Allegations

Claim Element (from Independent Claim 5) Alleged Infringing Functionality Complaint Citation Patent Citation
A central processing unit (CPU) comprising: ... a hardware accelerator to process stack-based instructions to produce an output that can be processed by the execute logic; The accused ARM processor cores are alleged to be CPUs containing hardware for Java acceleration, which processes stack-based Java bytecodes. ¶¶22-30 col. 4:45-50
an operand stack for the stack-based instructions, the operand stack being maintained in a register file as a ring buffer; The accused processors' alleged hardware acceleration capability is asserted to include an operand stack, which the claim requires to be implemented as a "ring buffer" in the register file. ¶¶22-30 col. 15:52-54
a bytecode buffer that receives stack-based instructions from the memory; and an instruction decode unit coupled to the bytecode buffer... The alleged hardware acceleration functionality implies a system for fetching and decoding bytecodes, which the claim requires to be performed by a "bytecode buffer" and "instruction decode unit." ¶¶22-30 col. 9:35-42

Identified Points of Contention

  • Technical Question: The complaint does not detail the architecture of the accused ARM cores. A key factual question will be whether these cores contain the specific structures recited in Claim 5, such as a "ring buffer" for the operand stack and a distinct "bytecode buffer" and "instruction decode unit," or if their architecture is different.
  • Scope Question: The term "ring buffer" has a specific meaning in computer science. The infringement analysis will depend on whether the stack management implementation in the accused processors meets the legal construction of this term.

V. Key Claim Terms for Construction

  • The Term: "operand stack ... in a first register file" (’362 Patent, Claim 1)

  • Context and Importance: This term is the core of the asserted invention in the ’362 patent. The infringement case depends on whether the accused processors' method for handling Java stack operations constitutes maintaining the stack "in" the processor's main register file, as opposed to in a separate memory or dedicated hardware. Practitioners may focus on this term because it defines the primary point of interaction between the software (Java stack) and hardware (CPU registers).

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification discusses storing "portions of the operand stack" in the register file, which could suggest that not all of the stack must reside there at all times (e.g., ’362 Patent, col. 4:56-58). This could be argued to cover any system that uses general-purpose registers to cache the top-of-stack.
    • Evidence for a Narrower Interpretation: The patent describes a specific system where the "Java™ CPU register file 48" is used to store stack values, which operates with an "overflow/underflow line 60" to memory (’362 Patent, col. 4:41-67; Fig. 3). This could support a narrower construction requiring this specific architectural arrangement.

  • The Term: "ring buffer" (’436 Patent, Claim 5)

  • Context and Importance: This term specifies the data structure for the operand stack. Its definition is critical because "ring buffer" implies a specific behavior (e.g., wrapping around from the end to the beginning) that may or may not be present in the accused processors. A narrow definition could allow the defendants to design around the claim.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent itself does not explicitly define "ring buffer." Plaintiff may argue it should be given its ordinary meaning to one of skill in the art, which could potentially cover a variety of circular queue implementations for managing the stack within a fixed set of registers.
    • Evidence for a Narrower Interpretation: The term is introduced in the ’436 patent claims without detailed support in the specification, which primarily relies on the disclosure of the parent ’362 patent. Defendants may argue that the lack of a specific "ring buffer" embodiment in the specification, which instead describes a more general stack management system (’362 Patent, Fig. 5), limits the term's scope or raises questions of written description and enablement for this specific structure.

VI. Other Allegations

  • Indirect Infringement: The complaint makes conclusory allegations of indirect infringement (Compl. ¶¶ 32, 36). It does not, however, plead specific facts to support the required elements of knowledge and intent for induced infringement, such as referencing user manuals or marketing materials that instruct on the infringing use.
  • Willful Infringement: The complaint alleges willful infringement "upon information and belief" (Compl. ¶¶ 33, 37). It does not allege any facts indicating pre-suit knowledge of the patents by the defendants, such as prior correspondence or litigation.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A central issue will be one of technical evidence: can the plaintiff demonstrate, through discovery and expert analysis, that the accused ARM processor cores—merely alleged to be "capable of Java hardware acceleration"—actually implement the specific architectural and methodological limitations of the asserted claims, such as maintaining an operand stack in a register file as a ring buffer? The complaint’s lack of detail on this point makes it a primary hurdle for the plaintiff.

  2. The case will also turn on a question of claim construction: will key terms like "operand stack ... in a first register file" and "ring buffer" be construed broadly to encompass any hardware architecture that caches stack data in registers, or will they be limited more narrowly to the specific overflow/underflow and circular queue-like systems arguably disclosed in the patent specifications? The outcome of this legal question will likely determine the scope of the patents and, consequently, whether the accused products infringe.