DCT

3:22-cv-02044

Cedar Lane Tech Inc v. Uniview Technology

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:22-cv-02044, N.D. Tex., 09/15/2022
  • Venue Allegations: Venue is asserted on the basis that Defendant, a Texas corporation, has an established place of business within the Northern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s digital imaging products infringe three patents related to methods and systems for efficiently interfacing image sensors with memory and processing components.
  • Technical Context: The technology at issue addresses the efficient management of digital image data as it moves from an image sensor to a processor or compression engine, a fundamental process in devices like digital cameras, scanners, and surveillance systems.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
1999-06-01 ’527 Patent Priority Date
2000-01-21 ’790 Patent Priority Date
2000-01-21 ’242 Patent Priority Date
2002-10-29 ’527 Patent Issue Date
2005-12-06 ’790 Patent Issue Date
2013-09-17 ’242 Patent Issue Date
2022-09-15 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," Issued 2002-10-29

The Invention Explained

  • Problem Addressed: The patent's background describes conventional digital imaging systems that require an "extra memory device," typically RAM, to act as a buffer between an analog-to-digital (A/D) converter and a JPEG compression integrated circuit (IC) (’527 Patent, col. 1:35-42). This extra component adds to the system's cost and complexity (’527 Patent, col. 1:53-57).
  • The Patented Solution: The invention proposes an interface module that eliminates this extra memory by managing the data flow more efficiently. The module’s read control device reads a specific number of image lines (e.g., eight lines) into an internal memory. An output control device then reads out formatted "image blocks" (e.g., 8x8 pixels) from that memory and sends them directly to the JPEG compression device. This provides the data in the block format required by the compression unit without needing a separate, intermediate buffer memory (’527 Patent, Abstract; col. 2:3-20).
  • Technical Importance: This design aimed to reduce the bill-of-materials cost and physical footprint of digital imaging products by integrating the buffering and formatting logic, thereby saving "an extra memory device originally required by JPEG compression means" (’527 Patent, col. 1:12-15).

Key Claims at a Glance

The complaint asserts infringement of "Exemplary '527 Patent Claims" identified in an exhibit incorporated by reference, which was not publicly filed with the complaint (Compl. ¶15). The patent’s independent claims are Claim 1 (a module) and Claim 8 (a method).

  • Independent Claim 1 recites a module comprising:
    • read control means for sequentially reading a predetermined number of image lines from an A/D converter and generating a control signal.
    • memory means for storing the predetermined number of image lines.
    • output control means for sequentially reading an image block from the memory means and forwarding it to a built-in memory of a JPEG compression means.
  • Independent Claim 8 recites a method comprising the steps of:
    • sequentially reading a predetermined number of image lines from an A/D converter.
    • storing those image lines in a memory means.
    • sequentially reading a predetermined size of image block from the memory means to a built-in memory device when compression is required.
  • The complaint reserves the right to assert other claims, including dependent claims (Compl. ¶13).

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," Issued 2005-12-06

The Invention Explained

  • Problem Addressed: The patent notes that the "video style output" from CMOS image sensors is often incompatible with the data interfaces of commercial microprocessors, requiring "additional glue logic" and interface circuitry (’790 Patent, col. 1:47-53). This external logic negates some of the cost and integration benefits of using CMOS technology (’790 Patent, col. 1:62-66).
  • The Patented Solution: The patent describes an interface, preferably integrated onto the same semiconductor die as the image sensor, to bridge this gap (’790 Patent, col. 2:25-30). The interface uses a memory (such as a first-in, first-out or "FIFO" buffer) to store image data from the sensor. When the amount of data in the memory reaches a certain level, a signal generator alerts the host processor (e.g., via an interrupt). A control circuit then manages the transfer of the buffered data to the system bus at a rate determined by the processor, decoupling the sensor's fixed data rate from the processor's data access rate (’790 Patent, Abstract).
  • Technical Importance: By integrating this interface, the invention allows a processor to access image data from a CMOS sensor directly and efficiently, simplifying system design and reducing cost for products built around such sensors (’790 Patent, col. 2:25-30).

Key Claims at a Glance

The complaint asserts infringement of "Exemplary '790 Patent Claims" identified in an exhibit incorporated by reference, which was not publicly filed with the complaint (Compl. ¶24). The patent’s independent claims include Claim 1 (an interface) and Claim 15 (an integrated circuit).

  • Independent Claim 1 recites an interface comprising:
    • a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals.
    • a signal generator for generating a signal for the processor system in response to the quantity of data in the memory.
    • a circuit for controlling the transfer of data from the memory at a rate determined by the processor system.
  • Independent Claim 15 recites an integrated circuit comprising:
    • an imaging array sensor integrated on a die.
    • an interface integrated on the die, where the interface includes a memory for storing image data and a circuit for controlling data transfer to a data bus.
  • The complaint reserves the right to assert other claims, including dependent claims (Compl. ¶19).

Multi-Patent Capsule: U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," Issued 2013-09-17

  • Technology Synopsis: As a divisional of the application that led to the ’790 Patent, this patent addresses the same technical problem of efficiently interfacing a CMOS image sensor with a host processor system (’242 Patent, Abstract; col. 1:13-17). The invention describes an integrated circuit with an on-die interface that includes a memory (e.g., a FIFO buffer) to store image data. A signal generator alerts the host system when a predetermined amount of data is buffered, and a control circuit manages the subsequent data transfer to the system bus (’242 Patent, Abstract).
  • Asserted Claims: The complaint asserts infringement of claims from an unprovided exhibit (Compl. ¶33). The patent's independent claims are method claims, including Claim 1 and Claim 14.
  • Accused Features: The complaint alleges that "Exemplary Defendant Products," identified in the unprovided Exhibit 6, infringe the patent (Compl. ¶¶ 28, 33).

III. The Accused Instrumentality

Product Identification

  • The complaint does not identify any specific accused products by name in its body. It refers generally to "Exemplary Defendant Products" that are identified in Exhibits 4, 5, and 6, which were incorporated by reference but not filed publicly (Compl. ¶¶13, 19, 28).

Functionality and Market Context

  • The complaint does not provide sufficient detail for analysis of the accused products' specific functionality, features, or market position. It makes only the general allegation that the products "practice the technology claimed" by the patents-in-suit (Compl. ¶¶15, 24, 33).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint incorporates by reference claim chart exhibits (Exhibits 4, 5, and 6) that were not included with the public filing. The following is a summary of the narrative infringement theories.

  • '527 Patent Infringement Allegations: The complaint alleges that Defendant directly infringes one or more claims of the ’527 Patent by making, using, selling, and importing the "Exemplary Defendant Products" (Compl. ¶13). It states that the charts in Exhibit 4 demonstrate how these products "satisfy all elements" of the asserted claims (Compl. ¶15). The theory of direct infringement is also based on alleged internal testing of the products by Defendant's employees (Compl. ¶14).
  • '790 Patent Infringement Allegations: The complaint alleges that Defendant directly infringes the ’790 Patent through its making, using, and selling of the "Exemplary Defendant Products" (Compl. ¶19). It also alleges induced infringement, stating on information and belief that Defendant's "product literature and website materials" instruct end users on how to use the products in a manner that infringes the patent (Compl. ¶22). The complaint asserts that Exhibit 5 contains charts demonstrating that the accused products meet all elements of the asserted claims (Compl. ¶24).
  • Identified Points of Contention:
    • Architectural Questions: A central dispute may concern whether the architecture of the accused products maps onto the specific structures of the claims. For the ’527 Patent, a question is whether the accused products contain distinct "means" that perform the claimed functions of buffering a "predetermined number of image lines" and then forwarding discrete "image blocks" to a compression engine.
    • Functional Questions: For the ’790 Patent, the analysis may focus on the trigger for data transfer. A key question is whether the accused products use a "signal generator" that is activated "in response to the quantity of data in the memory," as claimed, or if data transfer is controlled by a different mechanism, such as processor polling or a fixed-time scheduler. For claims requiring integration on a single die (e.g., ’790 Patent, Claim 15), the physical construction of the accused products will be a central factual issue.

V. Key Claim Terms for Construction

  • Term: "image block" (’527 Patent, Claim 1)

    • Context and Importance: The infringement analysis for the '527 Patent depends on whether the accused products are found to process and transmit data as a discrete "image block". The definition of this term will determine if a continuous data stream or line-by-line transfer could meet this limitation.
    • Intrinsic Evidence for a Broader Interpretation: A party could argue the term should be read broadly to mean any discrete portion of image data, as the claim language itself does not specify a size.
    • Intrinsic Evidence for a Narrower Interpretation: The specification repeatedly links the "image block" to the requirements of the downstream JPEG compression unit, giving the example of an "image block of 8x8 pixels" corresponding to the "basic compression unit" (’527 Patent, col. 1:40-42). This suggests the term implies a specific size and format matched to the compression algorithm.

  • Term: "in response to the quantity of data in the memory" (’790 Patent, Claim 1)

    • Context and Importance: This phrase is critical to the infringement theory for the '790 Patent, as it defines the causal trigger for alerting the processor. Practitioners may focus on this term because it distinguishes a reactive, buffer-aware system from a passively polled or scheduled one.
    • Intrinsic Evidence for a Broader Interpretation: The specification states the signal is generated when the interface "has an amount of data approaching the limits of its storage capacity," which could be argued to encompass predictive or scheduled systems designed around known fill rates (’790 Patent, col. 6:2-4).
    • Intrinsic Evidence for a Narrower Interpretation: The patent describes a specific embodiment where an "interrupt generator 48 compares the FIFO counter output S_c and the FIFO limit S_L," and if the count is greater than or equal to the limit, the signal is asserted (’790 Patent, col. 6:10-15; Fig. 2). This supports a narrower reading that requires a direct comparison between the data quantity and a set threshold to trigger the signal.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 Patents. The factual basis for inducement is Defendant's alleged distribution of "product literature and website materials" that instruct customers on using the accused products in an infringing manner (Compl. ¶¶ 22, 31).
  • Willful Infringement: The complaint alleges willful infringement based on post-suit conduct. It asserts that the filing and service of the complaint provides Defendant with "actual knowledge" of infringement and that any continued infringing activities thereafter are willful (Compl. ¶¶ 21-22, 30-31). No allegations of pre-suit knowledge are made.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. An Architectural Mapping Question: Does the internal architecture of the accused products, which are not identified in the complaint, map onto the specific data-handling systems claimed in the patents? For the ’527 patent, this involves determining if the products use a line-buffering and block-forwarding scheme. For the ’790 and ’242 patents, the core question is whether a signal alerts the host processor in direct response to the amount of data in a buffer.
  2. An Evidentiary Question of Equivalence: Without public claim charts or product details, a central issue for the court will be whether discovery uncovers evidence showing that the accused products' components perform the specific functions of the claimed elements. The case may hinge on whether the accused data transfer mechanisms are functionally equivalent to the claimed "signal generator" and control circuits, or if they operate on fundamentally different technical principles.
  3. A Definitional Scope Question: The outcome may depend on claim construction. A key question will be whether the term "in response to the quantity of data" ('790 patent) can be construed to cover systems that do not use a direct buffer-level trigger, and whether "image block" ('527 patent) requires a specific size and format tied to a downstream process or can read on more generic portions of data.