DCT

4:25-cv-00466

InnoMemory LLC v. Fitech Payments LLC

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: InnoMemory, LLC v. Fitech Payments LLC, 4:25-cv-00466, N.D. Tex., 04/28/2025
  • Venue Allegations: Venue is alleged to be proper based on Defendant maintaining an established place of business within the Northern District of Texas.
  • Core Dispute: Plaintiff alleges that unspecified products from Defendant infringe a patent related to methods for reducing power consumption in computer memory devices during refresh operations.
  • Technical Context: The patent addresses power-saving techniques in dynamic random-access memory (DRAM), a technology critical to battery life in portable electronic devices.
  • Key Procedural History: The patent-in-suit is a continuation of a prior application that issued as U.S. Patent No. 6,618,314, which may be relevant for determining the scope of the patent’s claims.

Case Timeline

Date Event
2002-03-04 Earliest Priority Date ('960 Patent)
2003-07-29 '960 Patent Application Filed
2006-06-06 '960 Patent Issued
2025-04-28 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

  • Patent Identification: U.S. Patent No. 7,057,960, “Method and architecture for reducing the power consumption for memory devices in refresh operations,” issued June 6, 2006.

The Invention Explained

  • Problem Addressed: In conventional dynamic random-access memory (DRAM), all memory cells must be periodically refreshed to retain data, even when the device is in a low-power standby mode. This constant refreshing of the entire memory array consumes significant power, which is a critical issue for battery-powered portable devices ('960 Patent, col. 1:26-35, 49-53).
  • The Patented Solution: The invention provides a method and architecture to reduce power consumption by refreshing only necessary portions, or sections, of the memory array instead of the entire chip. The system uses specific control signals to selectively enable the "periphery array circuits"—the support circuitry needed for a refresh—for only those sections of memory that are actively being refreshed, while leaving the circuitry for other sections disabled and consuming no power ('960 Patent, Abstract; col. 2:48-55). This selective activation is managed by a control circuit that can be programmed to refresh any combination of memory sections ('960 Patent, col. 8:4-8).
  • Technical Importance: This approach allows for a significant reduction in standby power current, directly impacting and extending the continuous standby time for battery-operated electronics ('960 Patent, col. 1:53-56).

Key Claims at a Glance

  • The complaint does not identify specific claims, instead referencing "Exemplary '960 Patent Claims" in an external exhibit (Compl. ¶11). Independent claim 1 is representative of the patented method.
  • Independent Claim 1 recites a method with the following essential elements:
    • Controlling "background operations" (such as refresh) in each of a "plurality of sections" of a memory array using one or more control signals.
    • Generating these control signals in response to a "programmable address signal."
    • The background operations can be enabled "simultaneously in two or more" sections, independently of any other section.
    • Presenting the control signals and "decoded address signals" to "periphery array circuits" of the memory sections.
  • The complaint reserves the right to assert additional claims, including by the doctrine of equivalents (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

The complaint does not name any specific accused products, referring to them generally as the "Exemplary Defendant Products" identified in charts within an attached exhibit (Compl. ¶11, 13).

Functionality and Market Context

The complaint provides no details about the functionality or market context of the accused products. It alleges that Defendant infringes by "making, using, offering to sell, selling and/or importing" the accused products, and by having its employees "internally test and use" them (Compl. ¶¶ 11-12). The identity of the defendant, Fitech Payments LLC, suggests the accused instrumentalities could be payment processing terminals or related hardware that contain memory components.

IV. Analysis of Infringement Allegations

The complaint alleges that infringement is detailed in claim charts provided as Exhibit 2 (Compl. ¶13). As this exhibit was not available for analysis, a detailed element-by-element comparison is not possible. The complaint's infringement theory is stated in conclusory terms, alleging that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" and "satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13). No probative visual evidence provided in complaint.

  • Identified Points of Contention:
    • Evidentiary Question: The complaint does not plead any specific facts linking the business of Fitech Payments (a payment processing company) to the low-level semiconductor architecture claimed in the ’960 Patent. A central issue will be whether the Plaintiff can produce evidence demonstrating that Defendant’s products contain memory chips and, further, that those chips operate using the specific sectional power-saving method required by the claims.
    • Technical Question: Assuming an infringing memory chip is identified, a key technical question will be whether its operation meets the claim limitation requiring that background operations "can be enabled simultaneously in two or more of said plurality of sections independently of any other section" ('960 Patent, col. 8:50-53). This requires a specific, programmable, and independent control capability that must be proven to exist in the accused products.

V. Key Claim Terms for Construction

  • Term: "background operations"

    • Context and Importance: This term defines the scope of the infringing activity. Claim 2 specifies that these operations "comprise a refresh operation," and claim 4 states they "comprise parity checking" ('960 Patent, col. 8:54-55, 59-60). The patent also mentions "housekeeping operations" (col. 8:22). The breadth of this term will be critical to determining if the functions performed by the accused devices fall within the claims.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification suggests the invention is not limited to refresh operations, stating it may be implemented to control "other background memory access operations and/or housekeeping operations" ('960 Patent, col. 8:21-23). This could support an argument that the term covers a range of internal memory management tasks.
      • Evidence for a Narrower Interpretation: The patent's title, abstract, and background section consistently and almost exclusively frame the invention in the context of "refresh operations" ('960 Patent, Title; Abstract; col. 1:11-13). A defendant may argue that this focus limits the term's scope primarily to memory refresh, and that other "operations" must be of a similar, power-intensive nature.

  • Term: "periphery array circuits"

    • Context and Importance: This term is at the technical heart of the invention, as it is the selective enablement of these circuits that achieves the power savings. Infringement will depend on identifying these specific circuit types in an accused device. Practitioners may focus on this term to dispute whether the accused device's architecture maps onto the claimed structure.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent describes these circuits functionally as "support circuits for sections being refreshed" ('960 Patent, col. 2:52-53). A plaintiff might argue that any support circuitry that is selectively activated for a memory section falls within this definition.
      • Evidence for a Narrower Interpretation: Dependent claim 5 provides an explicit list of such circuits, including "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 8:62-65). A defendant could argue this list defines and limits the scope of the term, or at least provides the definitive examples of what constitutes a "periphery array circuit." Figure 5 provides a detailed schematic of these specific circuits ('960 Patent, Fig. 5).

VI. Other Allegations

  • Willful Infringement: The complaint does not explicitly allege willful infringement or plead any facts related to Defendant's knowledge of the ’960 Patent. However, in the prayer for relief, it requests that the case be declared "exceptional" under 35 U.S.C. § 285, which is the statutory basis for awarding attorney's fees, often in cases of willful infringement or litigation misconduct (Compl. Prayer for Relief ¶ E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A primary issue will be evidentiary: can the Plaintiff bridge the apparent gap between the Defendant's business in payment processing and the patent's subject matter of semiconductor memory architecture? The case will likely depend on Plaintiff’s ability to present concrete evidence that specific hardware used by the Defendant contains memory devices that practice the claimed power-saving methods.
  • A core legal and technical question will be one of operational correspondence: assuming an accused memory device is identified, does it actually perform "background operations" by selectively and independently enabling "periphery array circuits" for different memory sections, as claimed? The dispute may focus on whether the accused device's power management is merely a standard, non-infringing feature or if it aligns with the specific, programmable, multi-section control architecture required by the patent.