Stcunm v. Taiwan Semiconductor Mfg Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Stcunm (New Mexico)
  • Defendant: Taiwan Semiconductor Manufacturing Company Limited (Taiwan); TSMC North America, Inc. (California)
  • Plaintiff’s Counsel: Parker, Bunt & Ainsworth, P.C.
• Case Identification: 6:19-cv-00261, W.D. Tex., 04/12/2019
• Venue Allegations: Venue is alleged to be proper for the foreign parent company, Taiwan Semiconductor Manufacturing Corporation Limited, in any U.S. judicial district. For the domestic subsidiary, TSMC North America, Inc., venue is based on its alleged physical location and "regular and established place of business" within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor manufacturing processes at various advanced technology nodes infringe a patent related to methods for growing non-silicon crystalline layers on silicon substrates.
• Technical Context: The technology addresses a fundamental challenge in semiconductor manufacturing: integrating higher-performance materials with traditional silicon-based processes to continue the pace of transistor scaling and performance improvements.
• Key Procedural History: The complaint asserts that Plaintiff, as an arm of the State of New Mexico, possesses sovereign immunity and does not waive this immunity for post-grant proceedings at the U.S. Patent and Trademark Office, such as inter partes review (IPR). This assertion could significantly impact the avenues available to the defendant for challenging the patent's validity. The complaint also alleges Defendant had knowledge of the patent since at least September 25, 2018, based on a written notice.

Case Timeline

Date	Event
2012-07-17	'400 Patent Priority Date
2015-09-22	'400 Patent Issue Date
2018-09-25	Date of alleged written notice to Defendants
2019-04-12	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,142,400 - "Method of Making a Heteroepitaxial Layer on a Seed Area"

• Patent Identification: U.S. Patent No. 9,142,400, “Method of Making a Heteroepitaxial Layer on a Seed Area,” issued September 22, 2015. (Compl. ¶18; ’400 Patent, cover).

The Invention Explained

• Problem Addressed: The patent’s background section describes the difficulty of integrating high-mobility materials (like III-V semiconductors) onto silicon substrates, which is a key goal for advancing beyond conventional silicon-only transistors. The primary obstacles are defects, such as dislocations, that arise from the mismatch in the crystal lattice structures and thermal properties between the silicon substrate and the "foreign" material being grown on top of it. (’400 Patent, col. 1:46-65).
• The Patented Solution: The invention proposes a method to grow a high-quality "heteroepitaxial" (dissimilar material) layer on a very small, nanometer-scale "seed area" formed on a raised "pedestal." By confining the initial crystal growth to a region smaller than the typical distance between defects (under 100 nm), the strain from the lattice mismatch can be accommodated without generating performance-degrading dislocations. The process uses a "selective growth mask" to precisely control where the new material grows. (’400 Patent, Abstract; col. 2:28-45). Figures 1A-1E illustrate the sequence of forming a pedestal (12), applying a mask (14), exposing a seed area (16), and growing the new layer (20). (’400 Patent, Figs. 1A-1E).
• Technical Importance: This technique offered a method to overcome the defect problem, potentially enabling the use of superior non-silicon materials within the existing, highly advanced silicon manufacturing ecosystem. (’400 Patent, col. 1:37-45).

Key Claims at a Glance

• The complaint asserts at least independent claim 1. (Compl. ¶25, ¶26).
• The essential elements of independent claim 1 are:
  • providing a semiconductor substrate;
  • forming a nanostructured pedestal on the substrate, with the pedestal's top surface forming a seed area having a linear dimension between about 10 nm and 100 nm;
  • providing a selective growth mask layer on the top and side surfaces of the pedestal;
  • removing a portion of the mask to expose the seed area;
  • selectively etching back the exposed top surface of the pedestal; and
  • growing a heteroepitaxial layer on the seed area.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are semiconductor devices manufactured by TSMC, and the processes used to make them, at several process nodes, including 7 nm, 10 nm, 12 nm, and 16 nm. (Compl. ¶23). The complaint specifically identifies the A9 chip, used in Apple’s iPhone 6s and 6s+ products, as an exemplary product made with an accused process. (Compl. ¶23, ¶26).

Functionality and Market Context

The accused instrumentalities are advanced semiconductor manufacturing processes that form the basis of TSMC’s foundry business. These processes are used to fabricate high-performance processors and other integrated circuits for third-party customers. (Compl. ¶23, ¶27). The complaint alleges that these processes employ the patented method to create transistors with heteroepitaxial layers, such as silicon germanium. (Compl. ¶25, ¶26).
No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

'400 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
providing a semiconductor substrate	Using a semiconductor substrate, such as silicon.	¶25	col. 12:28-29
forming a nanostructured pedestal... the top surface forming a seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm	Forming a nanostructured pedestal (e.g., silicon) on the substrate. The top surface of this pedestal has a seed area (e.g., a cavity etch) with a linear dimension of 10-100 nm (e.g., 16 nanometers).	¶25, ¶26	col. 12:30-34
providing a selective growth mask layer on the top surface and side surface of the pedestal	Providing a selective growth mask (e.g., silicon dioxide and/or silicon nitride) on the top and side surfaces of the pedestal.	¶26	col. 12:35-37
removing a portion of the selective growth mask layer to expose the seed area of the pedestal	Selectively removing the mask (e.g., by reactive ion etch) to expose the seed area.	¶26	col. 12:38-39
selectively etching back the exposed top surface of the pedestal	Selectively etching back the exposed top surface of the pedestal (e.g., by reactive ion etch).	¶26	col. 12:40-41
growing a heteroepitaxial layer on the seed area	Growing a heteroepitaxial layer (e.g., silicon germanium) on the seed area.	¶26	col. 12:42-43

Identified Points of Contention

• Scope Questions: A central question may be whether the "fin" structures in Defendant's modern FinFET processes fall within the scope of the term "nanostructured pedestal" as described in the '400 Patent. The court will need to determine if the patent's description of a pedestal is broad enough to read on the specific geometry and function of a transistor fin.
• Technical Questions: The infringement allegation depends on a specific sequence of manufacturing steps. A key factual question will be what evidence shows that Defendant's process includes the distinct step of "selectively etching back the exposed top surface of the pedestal" after exposing the seed area but before growing the new layer, as required by claim 1.

V. Key Claim Terms for Construction

The Term: "nanostructured pedestal"

• Context and Importance: The applicability of the patent to modern FinFET semiconductor processes likely hinges on the construction of this term. Practitioners may focus on this term because Defendant will likely argue that its transistor "fins" are structurally and functionally distinct from the "pedestals" disclosed in the patent.
• Evidence for a Broader Interpretation: The specification introduces pedestals simply as structures "formed on the substrate" for subsequent epitaxial growth, which could be argued as a broad functional definition. (’400 Patent, col. 5:4-5).
• Evidence for a Narrower Interpretation: The detailed description notes that for strain relief, "it is useful to have the pedestals roughly as high or higher as the smallest in-plane dimension of the seed area." (’400 Patent, col. 5:21-25). This language, tying the structure to a specific functional dimension and purpose, could support a narrower construction that may not read on all fin-like structures.

The Term: "selectively etching back the exposed top surface of the pedestal"

• Context and Importance: This term describes a specific, active process step that must be present in the accused process. Practitioners may focus on this term because it represents a potential point of non-infringement if Defendant's process achieves a similar result through a different step or omits this step entirely.
• Evidence for a Broader Interpretation: The patent states that "Suitable etch back processes are well known in the art," which could support construing the term to cover a range of known surface removal techniques. (’400 Patent, col. 5:60-61).
• Evidence for a Narrower Interpretation: This step is claimed separately from the prior step of "removing a portion of the selective growth mask layer," suggesting it is a distinct and additional action. (’400 Patent, col. 12:38-41). The patent figures also depict a clear, discrete material removal from the pedestal top (Fig. 1D), which may support an interpretation requiring a deliberate recessing of the surface, not just an incidental cleaning. (’400 Patent, Fig. 1C, Fig. 1D).

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement. The inducement theory is based on Defendant's "sales engineering and technical marketing efforts" that allegedly encouraged customers like Apple to use the infringing processes to obtain "design wins." (Compl. ¶27). The contributory infringement theory is based on Defendant providing manufacturing services and designs incorporating the heteroepitaxial layer, which is alleged to be a non-staple component especially adapted for infringing the patent. (Compl. ¶28).
• Willful Infringement: The willfulness allegation is based on alleged actual knowledge of the '400 Patent since at least September 25, 2018, the date of a purported notice letter. The complaint alleges that Defendants continued their infringing activities despite this knowledge and an objectively high likelihood of infringement. (Compl. ¶29, ¶30).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of structural scope: can the term "nanostructured pedestal," as defined in the patent, be construed to cover the "fin" architecture used in Defendant’s modern FinFET manufacturing processes, or is there a fundamental structural distinction?
• A key evidentiary question will be one of process verification: does the accused manufacturing process include the specific, discrete step of "selectively etching back" the top surface of the seed area after removing the mask but before growing the new layer, as explicitly required by the asserted claim?
• A significant procedural factor will be the effect of the Plaintiff's asserted sovereign immunity. The Plaintiff's claim that it is immune from administrative patent validity challenges at the USPTO (Compl. ¶8) could, if upheld, prevent Defendant from using inter partes review (IPR) proceedings, forcing all validity arguments to be litigated exclusively within the district court.