DCT
1:22-cv-00852
Katana Silicon Tech LLC v. GlobalFoundries Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Katana Silicon Technologies LLC (Texas)
- Defendant: GlobalFoundries, Inc. (Cayman Islands), GlobalFoundries U.S. Inc. (Delaware), and GlobalFoundries U.S. 2 LLC (Delaware)
- Plaintiff’s Counsel: Carter Arnett PLLC
- Case Identification: 6:22-cv-00191, W.D. Tex., 02/24/2022
- Venue Allegations: Venue is alleged to be proper because Defendants maintain a regular and established place of business in the district, specifically a regional office and design center in Austin, and have committed the alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor manufacturing processes and the resulting integrated circuits infringe two patents related to transistor structure and through-substrate interconnects.
- Technical Context: The technology concerns advanced semiconductor fabrication, including FinFET transistor architecture and Through-Silicon Vias (TSVs), which are fundamental to producing smaller, more powerful, and three-dimensionally integrated microchips.
- Key Procedural History: The complaint alleges that Defendant received pre-suit notice of infringement of the ’861 Patent on May 28, 2018, and of the ’903 Patent on January 28, 2021, which may form the basis for claims of willful infringement. The ’861 Patent expired on or about June 30, 2019.
Case Timeline
| Date | Event |
|---|---|
| 1998-06-30 | Priority Date for U.S. Patent No. 6,291,861 |
| 2001-09-18 | Issue Date for U.S. Patent No. 6,291,861 |
| 2003-01-22 | Priority Date for U.S. Patent No. 7,402,903 |
| 2008-07-22 | Issue Date for U.S. Patent No. 7,402,903 |
| 2018-05-28 | Date of alleged pre-suit notice for ’861 Patent |
| 2019-06-30 | Expiration Date for ’861 Patent |
| 2021-01-28 | Date of alleged pre-suit notice for ’903 Patent |
| 2022-02-24 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,291,861 - “SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME,” issued September 18, 2001.
The Invention Explained
- Problem Addressed: As transistors shrink, they become more susceptible to performance degradation from "short channel effects" like current leakage and voltage fluctuations. The patent notes that prior art methods for creating elevated source/drain structures to combat these issues suffered from low manufacturing yield due to "vertical stagger or protrusion of the gates" (’861 Patent, col. 1:13-19, col. 7:1-2).
- The Patented Solution: The invention describes a transistor structure where the source/drain regions are formed to extend over not only the active region but also a portion of the adjacent device separation (isolation) region. This creates a source/drain surface with a curved or slanted profile, which increases the surface area for electrical contacts and reduces parasitic capacitance and resistance, thereby improving transistor performance ('861 Patent, Abstract; col. 10:14-22).
- Technical Importance: This geometric approach provided a method to improve transistor performance and manufacturing yield for advanced semiconductor nodes by mitigating short-channel effects and parasitic losses ('861 Patent, col. 11:9-19).
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 1 (Compl. ¶33).
- Claim 1 Essential Elements:
- A semiconductor device with a device separation region and an active region.
- A gate with a gate dielectric film and a side wall spacer.
- A source/drain.
- A contact electrically coupled to the source/drain.
- The active region is in contact with the gate dielectric film at a "first surface," with a portion of the source/drain located above this first surface.
- The contact is in contact with the source/drain at a "second surface."
- The second surface passes through a specific segment connecting a point on the source/drain touching the separation region to a point on the source/drain touching the side wall spacer.
- The second surface constitutes an "angle with respect to the first surface."
- The complaint reserves the right to assert additional claims (Compl. ¶32).
U.S. Patent No. 7,402,903 - “SEMICONDUCTOR DEVICE,” issued July 22, 2008.
The Invention Explained
- Problem Addressed: In three-dimensionally stacked chips, forming reliable vertical interconnects ("through plugs" or TSVs) was challenging. Etching deep holes for these plugs through a substrate with varied materials (e.g., insulation films and diffusion layers) resulted in non-uniform etch speeds, leading to misshapen plugs and "defect[s] in terms of reliability" ('903 Patent, col. 1:42-47, col. 4:11-16).
- The Patented Solution: The invention proposes a device structure where the through plug is strategically placed to avoid etching through multiple material types simultaneously. The patent discloses forming the through plug so its side surface is surrounded by either the insulation film (without touching diffusion layers) or a diffusion layer (without touching the insulation film). This allows the etching process to proceed at a constant speed, "realizing processing with high shape controllability" ('903 Patent, col. 4:17-46).
- Technical Importance: This method improved the manufacturing productivity and reliability of through-plugs, a key enabling technology for the 3D integration of semiconductor devices ('903 Patent, col. 1:14-17).
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 8 (Compl. ¶65).
- Claim 8 Essential Elements:
- A semiconductor device with a substrate, diffusion layer patterns, and an insulation film between them.
- A pattern portion (e.g., metal wiring) formed above the diffusion layers/insulation film.
- A through plug formed to pass through the insulation film and the substrate.
- The through plug has a side surface in contact with the insulation film.
- Crucially, "the side surface being surrounded by the insulation film without being in contact with the diffusion layer patterns."
- The through plug is also partly surrounded by the pattern portion above.
- The complaint reserves the right to assert additional claims (Compl. ¶64).
III. The Accused Instrumentality
Product Identification
- For the ’861 Patent, the accused instrumentalities are integrated circuits manufactured using Defendant's 14 nm LPP FinFET, 12 nm LP FinFET, and 12 nm LP+ FinFET processes. An exemplary product identified is AMD's RADEON RX 480 graphics card (Compl. ¶¶ 31, 33).
- For the ’903 Patent, the accused instrumentalities are products employing Defendant’s TSV structure, exemplified by the GlobalFoundries 32 nm controller found within the Micron MT43A4G40200NFA-S15 ES A HMC (Hybrid Memory Cube) product (Compl. ¶¶ 63, 65).
Functionality and Market Context
- The accused FinFET processes involve creating transistors with a "slanted raised source/drain (S/D)" which allegedly "partially overlaps the isolation region," a feature accused of mapping to the ’861 Patent’s claims (Compl. ¶31). The complaint supports this with Transmission Electron Microscope (TEM) images of a PMOS transistor (Compl. ¶34, Fig. 1).
- The accused TSV structure is a vertical electrical interconnect passing through a silicon die, a technology essential for high-performance, 3D-stacked devices like the Hybrid Memory Cube (Compl. ¶¶ 59, 63). The complaint illustrates the accused structure with Scanning Electron Microscope (SEM) images (Compl. ¶66, Fig. 1-1).
IV. Analysis of Infringement Allegations
’6,291,861 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A semiconductor device (A) comprising a device separation region (B) and an active region (C) | The accused product is a semiconductor device with an isolation region (SiO) serving as the device separation region and a silicon fin (Si fin) serving as the active region. | ¶34, Fig. 1 | col. 2:15-18 |
| a portion of the source/drain being located above the first surface (J) | The raised source/drain (SiGe epi) is shown in a TEM image as being physically located above the surface of the active region. The complaint provides Figure 3, a cross-sectional image of the accused product showing the source/drain located above the first surface. | ¶36, Fig. 3 | col. 2:19-20 |
| the contact is in contact with the source/drain at a source/drain surface defining a second surface (K) | A contact is shown making electrical connection with the surface of the raised source/drain (SiGe). | ¶37, Fig. 4 | col. 2:20-21 |
| the second surface passing through a segment connecting a first point on the source/drain surface in contact with the device separation region to a second point on an edge of the source/drain surface in contact with the side wall spacer... (L) | The complaint alleges this geometric path exists on the surface of the accused product's slanted source/drain region, connecting the isolation region to the side wall spacer. | ¶37, Fig. 4 | col. 27:8-14 |
| constituting an angle with respect to the first surface (M) | The slanted nature of the raised source/drain region in the accused FinFET device is alleged to form an angle relative to the surface of the active region (the silicon fin). | ¶37, Fig. 4 | col. 2:21-22 |
’7,402,903 Infringement Allegations
| Claim Element (from Independent Claim 8) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor device comprising a semiconductor substrate (A); a plurality of diffusion layer patterns (B) formed on the semiconductor substrate; an insulation film formed between the diffusion layer patterns (C)... | The accused device is shown in an SEM image to contain a substrate, diffusion layers, and an insulation film between them. The complaint provides Figure 1-1, an SEM image showing these layers. | ¶66, Fig. 1-1 | col. 10:2-5 |
| a through plug (F) formed to... pass through the insulation film and the semiconductor substrate (I) | The accused device contains a TSV structure that serves as the through plug, which is shown in an SEM image to vertically traverse the device layers. | ¶68, Fig. 3 | col. 11:18-21 |
| the side surface being surrounded by the insulation film without being in contact with the diffusion layer patterns (H) | The complaint alleges, with a supporting SEM image, that the accused TSV is formed within the insulation film region such that its side surface does not touch the adjacent diffusion layer patterns. | ¶68, Fig. 3 | col. 11:34-37 |
| the through plug being partly surrounded by the pattern portion above the diffusion layer patterns and/or the insulation film and being insulated from the pattern portion (J) | The top of the TSV is shown to be surrounded by an overlying pattern portion (e.g., metal interconnect layers) from which it is electrically isolated. | ¶69, Fig. 4 | col. 11:37-41 |
Identified Points of Contention
- Scope Questions (’861 Patent): A primary issue may be whether the claim language of the ’861 patent, drafted with 2D-like transistor diagrams, can be properly mapped onto the accused 3D FinFET architecture. The definitions of "first surface" (of the active region) and the "angle" of the "second surface" (of the source/drain) will be central, raising the question of whether a FinFET’s topography fits within the patent’s geometric claims.
- Technical Questions (’903 Patent): The infringement analysis for the ’903 patent will likely turn on a key factual question: does the accused TSV structure meet the negative limitation of being "without being in contact with the diffusion layer patterns"? This will require detailed evidentiary analysis of the physical structure, as any contact, however incidental, could be argued by a defendant to defeat a literal infringement allegation.
V. Key Claim Terms for Construction
Patent: U.S. 6,291,861
- The Term: "a second surface ... constituting an angle with respect to the first surface" (Claim 1)
- Context and Importance: This term defines the core geometry of the claimed invention. The infringement case hinges on whether the slanted top surface of the accused FinFET's raised source/drain region satisfies this limitation. Practitioners may focus on this term because its interpretation will determine if the patent, depicted with planar-style embodiments, can read on modern 3D transistor structures.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the surface of the source/drain region as having a "curved and/or slanted profile" ('861 Patent, col. 4:25-28), which may support construing "angle" to include any non-parallel orientation, including the topography of the accused product.
- Evidence for a Narrower Interpretation: The patent’s figures, such as FIG. 1, depict a specific angular relationship in a non-FinFET structure. A defendant may argue that the claims should be limited to the disclosed embodiments, where the "first surface" is a flat plane on top of the substrate.
Patent: U.S. 7,402,903
- The Term: "without being in contact with the diffusion layer patterns" (Claim 8)
- Context and Importance: This negative limitation is dispositive for infringement. It describes one of the two configurations taught by the patent to achieve uniform etching. The entire infringement theory for claim 8 rests on proving that the accused TSV is physically isolated from the diffusion layers.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A plaintiff would likely argue for the plain and ordinary meaning of "without being in contact," meaning a lack of any physical touching, which the complaint's SEM images purport to show (Compl. ¶68, Fig. 3).
- Evidence for a Narrower Interpretation: A defendant might argue that the term should be interpreted in light of the problem solved—preventing non-uniform etching. The specification states that placing the plug in a uniform material (either insulation or diffusion layer) maintains a constant etching speed ('903 Patent, col. 4:17-46). A defendant could argue that if the accused structure achieves this goal, incidental or de minimis contact should not be considered "in contact" for infringement purposes.
VI. Other Allegations
Indirect Infringement
- The complaint alleges both induced and contributory infringement for both patents. It claims Defendant induced infringement by providing its customers with infringing semiconductor processes and products, along with technical documentation, data sheets, and user manuals that instruct on their use (Compl. ¶¶ 45, 47, 77, 79). It alleges contributory infringement by asserting the accused products are especially made for infringement and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶ 46, 78).
Willful Infringement
- The willfulness allegations for both patents are based on alleged pre-suit actual knowledge. The complaint cites specific notice letters sent to Defendant dated May 28, 2018 for the ’861 patent and January 28, 2021 for the ’903 patent (Compl. ¶¶ 38, 70). The complaint further alleges that Defendant’s infringement was "so obvious that it should have been known" given its sophistication and large patent portfolio in the same field (Compl. ¶¶ 41, 73).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technological translation: can the claims of the ’861 Patent, which describe and illustrate a raised source/drain structure in a planar-like transistor context, be construed to cover the distinct three-dimensional topography of the accused FinFET devices? The construction of key geometric terms like "first surface" and "angle" will be dispositive.
- A key evidentiary question will be one of physical compliance: does the accused Through-Silicon Via (TSV) meet the strict negative limitation of ’903 Patent's Claim 8, requiring it to be formed "without being in contact with the diffusion layer patterns"? The outcome will likely depend on competing expert analyses of high-resolution microscopy evidence.
- Finally, a central question for damages will be willfulness: did Defendant's alleged continued infringement after receiving specific notice letters in 2018 and 2021 constitute willful conduct, potentially exposing it to enhanced damages for both past infringement of the expired ’861 Patent and ongoing infringement of the ’903 Patent?