DCT

1:22-cv-00854

3D Surfaces LLC v. Dell Tech Inc

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:

  • Case Identification: 6:21-cv-01107, W.D. Tex., 10/25/2021

  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Dell maintains a regular and established place of business in the district and because a substantial part of the events giving rise to the claims, including acts of infringement, occurred there.

  • Core Dispute: Plaintiff alleges that Dell’s computers and other devices that support DirectX 11 and higher graphics technology infringe two patents related to real-time, hardware-based tessellation of 3D surfaces.

  • Technical Context: The technology concerns a fundamental process in computer graphics where complex, curved surfaces are efficiently broken down into simpler triangles for real-time rendering, a critical function for modern video games and 3D applications.

  • Key Procedural History: Plaintiff alleges it provided Defendant with notice of infringement of the first patent-in-suit as early as December 2009 and the second patent-in-suit as early as September 2011. The second patent is a reissue of a patent from the same family as the first, indicating a shared technical disclosure and prosecution lineage.

Case Timeline

Date Event
2000-07-28 Earliest Priority Date for '299 and '534 Patents
2007-07-17 U.S. Patent No. 7,245,299 Issued
2009-12-23 Alleged Notice Date to Dell for '299 Patent
2011-07-12 U.S. Patent No. RE42,534 Issued
2011-09-07 Alleged Notice Date to Dell for '534 Patent
2021-10-25 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,245,299 - "Bicubic Surface Real-Time Tesselation Unit"

  • Patent Identification: U.S. Patent No. 7,245,299, titled “Bicubic Surface Real-Time Tesselation Unit,” issued July 17, 2007 (’299 Patent, front page; Compl. ¶10).

The Invention Explained

  • Problem Addressed: The patent’s background describes the inefficiency of conventional "off-line tessellation," where complex surfaces were converted into a fixed-resolution mesh of triangles before rendering. This approach was computationally expensive and resulted in suboptimal image quality, as distant objects were over-detailed while close objects could appear blocky or like a "polyhedron" (’299 Patent, col. 2:50-65, col. 3:1-4). This also created a high-bandwidth requirement for the bus between the CPU and the Graphics Processing Unit (GPU) (’299 Patent, col. 3:5-12).
  • The Patented Solution: The invention proposes moving the tessellation process into a dedicated hardware "tessellate unit" within the GPU itself (’299 Patent, Fig. 3). This unit is designed to receive high-level surface descriptions (e.g., control points for bicubic patches) from the CPU and dynamically generate the appropriate number of triangles in real-time. The level of detail is determined by criteria measured in "screen coordinates," allowing the system to generate more triangles for objects close to the viewer and fewer for those far away, a capability described as "automatic level of detail" (’299 Patent, col. 5:9-18).
  • Technical Importance: This on-the-fly, adaptive approach to tessellation aimed to solve major performance bottlenecks in 3D graphics by reducing CPU-GPU data transfer and optimizing rendering workload based on the final view. (’299 Patent, col. 5:19-29).

Key Claims at a Glance

  • The complaint asserts independent claim 11 (Compl. ¶16).
  • The essential elements of claim 11 are:
    • A system with a processor and a coupled GPU.
    • The GPU comprises a transform unit, a lighting unit, a renderer unit, and a tessellate unit coupled between the transform and lighting units.
    • The processor transmits objects to the GPU as "control points."
    • The transform unit transforms the control points.
    • The tessellate unit executes instructions for real-time tessellation of rational and non-rational surfaces.
    • The lighting unit lights the vertices of the resulting triangles.
    • The renderer unit renders the triangles by executing a second set of instructions.

U.S. Reissue Patent No. RE42,534 - "Bicubic Surface Real-Time Tesselation Unit"

  • Patent Identification: U.S. Patent No. RE42,534, titled “Bicubic Surface Real-Time Tesselation Unit,” issued July 12, 2011 (’534 Patent, front page; Compl. ¶11).

The Invention Explained

  • Problem Addressed: As a reissue of a patent in the same family as the ’299 Patent, the ’534 Patent addresses the same technical problem: the performance limitations and visual artifacts associated with static, off-line tessellation in real-time 3D graphics (’534 Patent, col. 2:58-65, col. 3:1-12).
  • The Patented Solution: The patent describes a method for real-time graphics rendering that relies on a hardware architecture featuring a "tessellate unit" situated between a "transform unit" and a "lighting unit" (’534 Patent, Fig. 3). This architecture enables the system to receive high-level object descriptions and dynamically subdivide them into triangles for rendering, with the subdivision level being adaptable to the object's distance from the viewer (’534 Patent, col. 5:25-34).
  • Technical Importance: This method provided a pathway to more efficient and visually sophisticated real-time 3D rendering by integrating adaptive tessellation directly into the graphics hardware pipeline. (’534 Patent, col. 5:25-44).

Key Claims at a Glance

  • The complaint asserts independent claim 15 (Compl. ¶40).
  • The essential elements of claim 15 are a method comprising the steps of:
    • Providing a tessellation unit coupled between a transform unit and a lighting unit.
    • Receiving graphic objects to be rendered.
    • Transforming the graphic objects using the transform unit.
    • Tessellating the transformed objects using the tessellation unit.
    • Lighting the vertices of triangles resulting from the tessellation using the lighting unit.

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the "Accused Products" as a wide range of Dell computers, including laptops (e.g., Alienware, XPS, Latitude), tablets, 2-in-1s, and desktops that "support DirectX 11 and higher 3D graphics technology" (Compl. ¶14). The allegations specifically target products containing Intel Core processors (4th gen and later) or AMD processors with integrated GPUs capable of supporting DirectX 11.1 and higher (Compl. ¶17, ¶41).

Functionality and Market Context

  • The accused functionality resides within the GPUs of these products, which the complaint alleges implement a graphics pipeline conforming to the DirectX 11 (and higher) standard (Compl. ¶17). This standard introduced new, programmable pipeline stages for hardware tessellation, which the complaint maps to the patented invention (Compl. ¶23). The complaint presents a die image from an Intel technical document to illustrate that the accused products contain a microprocessor with both a CPU and an integrated GPU on the same semiconductor die (Compl. p. 5, ¶18). The complaint alleges these products are commercially significant, particularly in the gaming market with brands like Alienware (Compl. p. 4).

IV. Analysis of Infringement Allegations

’299 Patent Infringement Allegations

Claim Element (from Independent Claim 11) Alleged Infringing Functionality Complaint Citation Patent Citation
A system, comprising: a processor; and a graphics processing unit (GPU) coupled to the processor... The Accused Products are computer systems with a microprocessor (CPU) and an integrated GPU coupled via an on-die bus like the "SoC Ring Interconnect." ¶18, ¶19 col. 7:4-6
...the GPU comprising a transform unit, a lighting unit, a renderer unit, and a tessellate unit coupled between the transform unit and the lighting unit; The DirectX 11-capable GPU allegedly contains a "Vertex Shader" (transform unit), a "Hull Shader, Tessellator and Domain Shader" (tessellate unit), a "Rasterizer and Pixel Shader" (lighting unit), and an "Output Merger" (renderer unit), arranged in the claimed sequence. The complaint uses an annotated diagram of the Direct3D 11 pipeline to illustrate this alleged structure. ¶19, ¶22-¶25, p. 9 col. 7:6-9
wherein the processor transmits objects to be rendered to the GPU as control points, The CPU is alleged to transmit objects to be rendered, such as primitives for a patch, to the GPU as "control points." ¶26, ¶27 col. 7:10-12
the transform unit transforms the control points, The GPU's Vertex Shader allegedly functions as the transform unit, taking control points as input and transforming them into vertices. ¶22, ¶28 col. 7:12-14
the tessellate unit executes a first set of instructions for tessellating both rational and non-rational object surfaces in real-time The combination of the Hull, Tessellator, and Domain shader stages is alleged to be the tessellate unit, which performs real-time tessellation of various surface types, including Bezier patches and NURBS. ¶29 col. 7:8-9
the lighting unit lights vertices of the triangles, and The Rasterizer and Pixel Shader stages are alleged to function as the lighting unit, which calculates lighting for the vertices of the triangles produced by tessellation. ¶24, ¶31 col. 11:57-58
the renderer unit renders the triangles by executing a second set of instructions. The Output Merger stage is alleged to be the renderer unit that generates the final pixel color, thereby rendering the triangles. ¶25, ¶32 col. 11:58-60

’534 Patent Infringement Allegations

Claim Element (from Independent Claim 15) Alleged Infringing Functionality Complaint Citation Patent Citation
A method comprising: providing a tessellation unit coupled between a transform unit and a lighting unit; The Accused Products allegedly perform a method that provides a GPU with a DirectX 11 pipeline. The complaint alleges this pipeline contains a tessellation unit (Hull/Tessellator/Domain Shaders) operatively coupled between a transform unit (Vertex Shader) and a lighting unit (Rasterizer/Pixel Shader). An annotated block diagram from an Intel manual is provided to support this structural allegation. ¶42, ¶43, ¶44, p. 25 col. 13:4-7
receiving graphic objects to be rendered by a graphics processing unit; The GPU in the Accused Products receives graphic objects (primitives) transmitted from the CPU over a bus. ¶45 col. 15:13-15
transforming the graphic objects into transformed objects using said transform unit; The Vertex Shader is alleged to be the transform unit that transforms incoming control points into vertices. ¶46 col. 15:16-17
tessellating the transformed objects using said tessellation unit; and The Hull, Tessellator, and Domain Shader stages are alleged to be the tessellation unit that performs real-time tessellation on the transformed objects. ¶47 col. 15:18-20
lighting vertices of triangles resultant from said tessellating using said lighting unit. The Rasterizer and Pixel Shader are alleged to be the lighting unit that lights the triangles produced by the tessellation process. ¶48 col. 16:1-2

Identified Points of Contention

  • Structural vs. Functional Equivalence: A primary question for both patents is whether the programmable shader stages in the accused DirectX 11 pipeline (e.g., Vertex Shader, Hull Shader) constitute the claimed hardware "units." The patents' figures depict these as distinct blocks (’299 Patent, Fig. 3), raising the question of whether a programmable, multi-purpose shader engine executing different programs constitutes the claimed structure or is merely functionally equivalent.
  • Scope of "Control Points": The ’299 Patent claims a system where the processor transmits "control points." The patent specification is heavily grounded in the context of "bicubic surfaces" defined by such points (’299 Patent, col. 2:36-41). A potential dispute is whether the term reads on the more generic "primitives" or vertex data streams that the complaint alleges are transmitted in the accused systems (Compl. ¶21, ¶27).

V. Key Claim Terms for Construction

  • The Term: "tessellate unit"

    • Context and Importance: This term is central to the invention's contribution. The dispute will likely focus on whether this term requires a dedicated, fixed-function hardware block as depicted in the patent figures, or if it can be construed to cover the sequence of programmable shader stages (Hull, Tessellator, Domain) that perform tessellation in the accused DirectX 11 pipeline. Practitioners may focus on this term because its construction could resolve whether a flexible, software-defined pipeline infringes a claim that appears to recite a specific hardware architecture.
    • Intrinsic Evidence for a Broader Interpretation: The specification describes the unit by its function: "for tessellating both rational and non-rational object surfaces in real-time" (’299 Patent, col. 7:8-9). This functional language may support an interpretation where any structure that performs this function infringes.
    • Intrinsic Evidence for a Narrower Interpretation: Figure 3 in both patents depicts the "Tesselate Unit" as a discrete block (9) separate from the "Transform" (2) and "Light" (3) units. The summary of the invention also lists the "tessellate unit" as a distinct component of the GPU alongside the other units, which may support a structural limitation (’299 Patent, col. 4:60-65).

  • The Term: "real-time"

    • Context and Importance: This term, appearing in claim 11 of the ’299 Patent and central to the ’534 Patent's disclosure, qualifies the tessellation process. Its definition will be important for determining infringement. The key question is whether "real-time" simply means "on-the-fly" during rendering, as opposed to pre-processing, or if it is implicitly tied to the specific performance-enhancing techniques disclosed in the patent.
    • Intrinsic Evidence for a Broader Interpretation: The background consistently contrasts the invention with "off-line tessellation," suggesting "real-time" is meant to distinguish the invention's dynamic, during-rendering approach from prior art pre-processing methods (’299 Patent, col. 2:50-58).
    • Intrinsic Evidence for a Narrower Interpretation: The patent attributes its "real-time" capability to specific methods, such as reducing the subdivision to two orthogonal curves and using screen-space criteria to minimize computations (’299 Patent, col. 5:5-18). A party could argue the term is not merely a result but is defined by the novel method used to achieve it.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for both patents. Inducement is predicated on Dell's alleged pre-suit knowledge (from 2009 and 2011 notices) and its subsequent actions of advertising, selling, and providing instructional materials for the Accused Products, which allegedly encourage users to perform the infringing methods (Compl. ¶¶33, 49). Contributory infringement is based on the allegation that the accused GPUs are a material component, especially made for infringement, and not a staple article of commerce with substantial non-infringing uses (Compl. ¶¶34, 50).
  • Willful Infringement: Willfulness is alleged based on Dell's purported knowledge of the patents since at least 2009 and 2011. The complaint claims that Dell, being aware of the infringement, "opted to make the business decision to 'efficiently infringe'" instead of licensing the technology, thereby acting willfully (Compl. ¶¶35, 51).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of claim scope and architecture: Can the programmable shader stages of the modern, flexible DirectX 11 pipeline be read to infringe claims for a system of discrete hardware "units" (transform, tessellate, lighting) as depicted and described in the patents, or is there a fundamental mismatch between the claimed architecture and the accused implementation?
  • A second central question will be one of indirect liability: As the direct infringer of the asserted method claim is the end-user, Plaintiff's case will depend on its ability to prove Dell possessed the specific intent to induce infringement, a question that will turn on the alleged pre-suit notice and the content of Dell's marketing, user manuals, and technical support for its graphics-capable computers.
  • A final key evidentiary question will be one of technical operation: Does the complaint provide sufficient evidence that the accused systems process "control points" and "both rational and non-rational object surfaces" in the manner required by the claims, or will discovery reveal a technical distinction between the specific bicubic surface processing described in the patents and the general-purpose triangle rasterization performed by the accused products?