DCT

1:22-cv-01095

ThroughPuter Inc v. Amazon Web Services Inc

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I. Executive Summary and Procedural Information

  • Case Name: ThroughPuter, Inc. v. Amazon Web Services, Inc.
  • Parties & Counsel:
  • Case Identification: 1:22-cv-01095, W.D. Tex., 08/04/2023
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains a regular and established place of business in Austin, including offices and fulfillment centers, and has actively recruited for positions directly related to the accused technology in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s EC2/F1 Platform, which provides cloud-based access to reconfigurable FPGA hardware, infringes patents related to configurable logic platforms that manage access and resources for multiple, concurrent applications.
  • Technical Context: The technology concerns the use of Field Programmable Gate Arrays (FPGAs) in cloud computing environments to provide hardware acceleration, a method for increasing processing speed and power efficiency for specialized computational tasks.
  • Key Procedural History: The complaint alleges that patents filed by Defendant's affiliate, Amazon Technologies, Inc., describe and claim technology substantially identical to that claimed in the patents-in-suit, but with later priority dates. Plaintiff presents side-by-side claim comparisons to support this allegation, which may be intended to address potential defenses regarding independent invention and to support allegations of willfulness. The original complaint in this matter was filed on October 27, 2022, establishing a date for alleged notice.

Case Timeline

Date Event
2013-08-23 Earliest Priority Date (’556, ’934, and ’682 Patents)
2016-11-30 AWS EC2 F1 Instances Launched
2022-05-31 U.S. Patent No. 11,347,556 Issued
2022-07-12 U.S. Patent No. 11,385,934 Issued
2022-10-27 Original Complaint Filed
2022-11-15 U.S. Patent No. 11,500,682 Issued
2023-08-04 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,347,556 - "Configurable Logic Platform With Reconfigurable Processing Circuitry"

  • Patent Identification: U.S. Patent No. 11,347,556, "Configurable Logic Platform With Reconfigurable Processing Circuitry," issued May 31, 2022 (Compl. ¶67).

The Invention Explained

  • Problem Addressed: The patent’s background describes the technical challenge of efficiently managing the execution of multiple, concurrent software programs on shared parallel processing hardware, noting that conventional software-based approaches do not scale well and consume significant processing resources (’556 Patent, col. 1:49-2:8). This problem is particularly acute in cloud computing, where maximizing both individual application performance and overall system utilization is critical (Compl. ¶31-33).
  • The Patented Solution: The invention is a hardware-based configurable logic platform with multiple, distinct reconfigurable regions. The platform provides dedicated hardware "interface functions" and a "reconfiguration logic function" that act as secure gateways between a host processor and the reconfigurable regions. This architecture is designed to provide secure, isolated, and concurrent execution for different applications, with hardware logic managing resource allocation (such as I/O bandwidth) and preventing direct, unrestricted access between the user-configured logic and the system's physical interconnect (’556 Patent, Abstract; col. 3:26-4:6).
  • Technical Importance: This architectural approach sought to resolve the inherent tension in cloud computing between accelerating single programs and efficiently utilizing a shared pool of resources (Compl. ¶32).

Key Claims at a Glance

  • The complaint asserts independent Claim 1 (Compl. ¶70).
  • The essential elements of Claim 1 are:
    • A configurable logic platform comprising a physical interconnect, a first reconfigurable logic region, and a second reconfigurable logic region.
    • A configuration port for applying configuration data to the regions.
    • A "reconfiguration logic function" accessible via the interconnect that provides restricted access to the configuration port.
    • A "first interface function" and a "second interface function," each providing an interface to its respective reconfigurable region while preventing that region from directly accessing the physical interconnect.
    • "Logic configured to apportion bandwidth" of the interconnect among the interface functions.
  • The complaint reserves the right to assert additional claims (Compl. ¶99).

U.S. Patent No. 11,385,934 - "Configurable Logic Platform With Reconfigurable Processing Circuitry"

  • Patent Identification: U.S. Patent No. 11,385,934, "Configurable Logic Platform With Reconfigurable Processing Circuitry," issued July 12, 2022 (Compl. ¶111).

The Invention Explained

  • Problem Addressed: The patent addresses the need for inventions that enable scalable, secure, and reliable dynamic execution of multiple applications on shared parallel processing systems, a key challenge for the scalability of the cloud computing model (’934 Patent, col. 2:10-24).
  • The Patented Solution: The patent describes a configurable logic platform built on an FPGA. The core of the solution is the implementation of both a "reconfiguration logic function" and an "interface function" within the FPGA's own reconfigurable logic. The reconfiguration function serves as a secure, restricted control plane for loading configuration data, while the interface function provides a separate data plane for communication that "prevents the reconfigurable logic region from directly accessing the physical interconnect." This hardware-enforced separation of control and data planes within the reconfigurable fabric itself creates a secure container for custom application logic (’934 Patent, Abstract).
  • Technical Importance: This architecture provides a hardware-based "shell" that can securely encapsulate multi-tenant logic on a shared FPGA, a foundational requirement for offering reconfigurable computing as a secure cloud service (Compl. ¶36-37).

Key Claims at a Glance

  • The complaint asserts independent Claim 1 (Compl. ¶114).
  • The essential elements of Claim 1 are:
    • A configurable logic platform comprising a physical interconnect and a reconfigurable logic region of an FPGA.
    • A configuration port for applying configuration data.
    • A "reconfiguration logic function" accessible via the interconnect that provides restricted access to the configuration port.
    • An "interface function" that allows information transfer over the interconnect but "prevents the reconfigurable logic region from directly accessing" it.
    • A "wherein" clause requiring that the reconfiguration logic function is implemented in the reconfigurable logic region.
  • The complaint reserves the right to assert additional claims (Compl. ¶137).

U.S. Patent No. 11,500,682 - "Configurable Logic Platform With Reconfigurable Processing Circuitry"

  • Patent Identification: U.S. Patent No. 11,500,682, "Configurable Logic Platform With Reconfigurable Processing Circuitry," issued November 15, 2022 (Compl. ¶149).
  • Technology Synopsis: This patent discloses an apparatus with a plurality of reconfigurable logic regions, each designed to implement a specific application logic. The invention features "logic for separately encapsulating" these regions, where this encapsulating logic includes a host interface that arbitrates between the different application logics and enforces a programmed apportionment of data transfer bandwidth over the physical interconnect (’682 Patent, Abstract). The technology provides a hardware mechanism for managing and isolating multiple application accelerators on a single configurable device while ensuring fair access to system I/O resources.
  • Asserted Claims: Independent Claim 1 is asserted (Compl. ¶152).
  • Accused Features: The complaint alleges the EC2/F1 Platform, with its multiple FPGAs, embodies the claimed apparatus. The "AWS FPGA Shell" is accused of being the "logic for separately encapsulating" the regions, and the PCIe bridge is alleged to be part of the host interface that arbitrates and apportions bandwidth among the FPGAs (Compl. ¶157-160).

III. The Accused Instrumentality

Product Identification

  • The Amazon Web Services (AWS) Elastic Compute Cloud (EC2) F1 server instances, referred to as the "EC2/F1 Platform" (Compl. ¶43).

Functionality and Market Context

  • The EC2/F1 Platform is a cloud computing service that provides users with access to server instances equipped with FPGAs for hardware acceleration (Compl. ¶74). Users can develop custom logic, register it as an "Amazon FPGA Image" (AFI), and deploy it to the FPGAs to accelerate workloads such as video processing, genomics, and financial analysis (Compl. ¶74; Ex. 17 at 1).
  • The platform architecture includes host CPUs connected to one or more FPGAs via a Peripheral Component Interconnect Express (PCIe) physical interconnect (Compl. ¶75). AWS provides an "AWS FPGA Shell" which encapsulates the customer's logic, creating a standardized interface between the custom logic, the host CPU, and other FPGA resources (Compl. ¶78, ¶82). A screenshot from an AWS presentation shows a diagram of the FPGA acceleration architecture, illustrating the relationship between the CPU, PCIe interconnect, and the FPGA loaded with an AFI (Compl. p. 22). The platform is marketed as a way to achieve significant performance improvements over CPU-only instances for certain applications (Compl. Ex. 17 at 1).

IV. Analysis of Infringement Allegations

11,347,556 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a physical interconnect for connecting the configurable logic platform to a processor The EC2/F1 Platform uses a PCIe physical interconnect to connect the FPGAs to the host CPU. ¶75 col. 21:41-43
a first reconfigurable logic region...and...a second reconfigurable logic region EC2 F1 instances contain multiple FPGAs, such as the eight FPGAs in an f1.16xlarge instance, each providing a customer-configurable logic region. ¶76 col. 21:44-49
a configuration port for applying the first and second configuration data The AWS FPGA Shell includes an SDA AXI-L interface port used to apply configuration data, in the form of Amazon FPGA Images (AFIs), to the reconfigurable logic regions. ¶77-78 col. 22:50-58
a reconfiguration logic function accessible via transactions of the physical interconnect...providing restricted access to the configuration port from the physical interconnect The platform's "MGT PF reconfiguration logic function," part of the PCIe logic, is accessible via the PCIe interconnect and restricts direct customer access to configuration, which is managed through protected AWS tools. A diagram from an AWS webinar shows the "MGT PF" as part of the FPGA Shell architecture (Compl. p. 24). ¶79-80 col. 22:59-64
a first interface function...and...a second interface function...provid[ing] an interface...and prevent[ing] the...logic region from directly accessing the physical interconnect The AWS FPGA Shell provides the interface for customer logic, which is accessible via DMA transactions over the PCIe interconnect, but prevents the customer logic from accessing the PCIe interconnect directly. A presentation slide titled "Abstracting FPGA I/O" illustrates this shell-based separation (Compl. p. 26). ¶82 col. 22:65-23:11
logic configured to apportion bandwidth of the physical interconnect The complaint alleges that functions described in Amazon's own U.S. Patent No. 11,182,320, including "arbitration logic... for apportioning bandwidth," are deployed in the EC2/F1 Platform's host interface to manage bandwidth among the multiple FPGAs. ¶83, ¶86-87 col. 23:12-15
  • Identified Points of Contention:
    • Technical Questions: A primary technical question may be whether the EC2/F1 Platform actually contains the "logic configured to apportion bandwidth" as claimed. The complaint's allegation relies on an inference that technology described in a separate Amazon patent is implemented in the accused product, as it concedes the "internal workings of the AWS FPGA Shell are not disclosed publicly" (Compl. ¶83). The functional reality of the accused product's bandwidth management will be a central factual dispute.
    • Scope Questions: A question of claim scope may arise regarding the meaning of "prevents the... region from directly accessing the physical interconnect." The dispute could center on whether providing a mediated, API-driven access method (like DMA through the shell) constitutes "preventing" direct access, or if the term requires a more absolute hardware-level blockade of certain transaction types.

11,385,934 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a physical interconnect for connecting the configurable logic platform to a processor The EC2/F1 Platform comprises a PCIe physical interconnect that connects the FPGA to the host CPU. A diagram from an AWS presentation illustrates this connection (Compl. p. 36). ¶119 col. 27:62-64
a reconfigurable logic region of an FPGA comprising logic blocks that are configured based on configuration data Each EC2 F1 instance contains one or more FPGAs with customer-configurable logic regions, described as having millions of programmable logic cells. ¶120 col. 27:65-67
a configuration port for applying the configuration data AWS stores configuration data as AFIs and applies it to the FPGAs via an SDA AXI-L interface port within the AWS FPGA Shell. ¶121-122 col. 28:1-4
a reconfiguration logic function...providing only restricted access to the configuration port from the physical interconnect The management reconfiguration logic ("MgmtPF") within the AWS FPGA Shell restricts access to customer logic reconfiguration to authorized AWS tools, which communicate through a protected Linux Kernel and the PCIe interconnect. A diagram illustrates this software/hardware stack (Compl. p. 39). ¶123-124 col. 28:5-10
an interface function...which...prevents the reconfigurable logic region from directly accessing the physical interconnect Customer logic regions must communicate through the AWS FPGA Shell, which provides a secure I/O interface and prevents the customer logic from directly accessing the PCIe interconnect. ¶126 col. 28:11-16
wherein the reconfiguration logic function is implemented in the reconfigurable logic region The complaint alleges that the AWS FPGA Shell, which contains the reconfiguration logic function, is itself programmed into sections of the FPGA's reconfigurable logic regions by AWS. ¶127 col. 28:17-19
  • Identified Points of Contention:
    • Technical Questions: A key question will be what specific hardware and/or software components constitute the "AWS FPGA Shell" and whether those components perform the functions of both the "reconfiguration logic function" and the "interface function" as claimed. Evidence regarding the actual implementation of the shell will be critical.
    • Scope Questions: The construction of "implemented in the reconfigurable logic region" will be central. This raises the question of whether a function must be realized entirely within the user-programmable FPGA fabric to meet this limitation, or if it can be a combination of pre-configured logic blocks, hard IP blocks on the FPGA, and firmware that do not reside in the reconfigurable fabric itself.

V. Key Claim Terms for Construction

  • The Term: "reconfiguration logic function" and "interface function" (’556 and ’934 Patents)

  • Context and Importance: The plaintiff's infringement theory maps these claimed functional blocks directly onto components of the accused "AWS FPGA Shell." The definition of these terms—specifically, whether they require a pure hardware implementation or can encompass firmware or software components, and their precise inputs and outputs—is critical to determining if the architecture of the accused platform aligns with the claim limitations.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claims recite these elements in functional terms ("a... function... providing..."), which may support a construction that is not limited to a specific hardware structure, as long as the recited function is performed (Compl. ¶70, ¶114). The specification describes the need to solve problems created by "system software," potentially suggesting that any non-software, hardware-based solution falls within the invention's scope (’556 Patent, col. 1:53-65).
    • Evidence for a Narrower Interpretation: The patents' abstracts and summaries repeatedly emphasize a solution implemented in hardware logic to achieve security and scalability (’934 Patent, Abstract). The "wherein" clause of Claim 1 of the ’934 Patent requires the "reconfiguration logic function" to be "implemented in the reconfigurable logic region," which may support a narrower construction limiting the function's location to the FPGA's programmable fabric itself (’934 Patent, col. 28:17-19).

  • The Term: "prevents the... logic region from directly accessing the physical interconnect" (’556 and ’934 Patents)

  • Context and Importance: This negative limitation is foundational to the patents' claimed security and isolation features. The case may turn on whether the AWS Shell's mediation of access to the PCIe bus qualifies as "preventing" direct access. Practitioners may focus on this term because it distinguishes a simple passthrough interface from a secure, managed one.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification's objective is to provide architectural security and reliability (’934 Patent, col. 2:21-24). This purpose could support reading "prevents" to mean any hardware-enforced mediation or abstraction layer that enforces rules and isolates tenant logic, rather than requiring a complete physical blockade.
    • Evidence for a Narrower Interpretation: The term "directly accessing" could be construed to mean making raw, unmediated bus-level requests. Embodiments described in the specification may disclose specific hardware gates or logic that physically block certain transaction types, which would support a narrower definition requiring more than just an API-level abstraction.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement under 35 U.S.C. § 271(b). It asserts that AWS encourages and instructs customers, developers, and partners to use the EC2/F1 Platform in a manner that directly infringes the patents. This allegation is supported by references to AWS's public-facing materials, including its website, tutorials, development kits, documentation, webinars, and white papers, which allegedly guide users on how to configure and deploy AFIs on the accused platform (Compl. ¶102-103, ¶140-141).
  • Willful Infringement: Willfulness is alleged based on Defendant’s knowledge of the patents since at least the filing date of the original complaint on October 27, 2022 (for the ’556 and ’934 Patents) and the issue date of November 15, 2022 (for the ’682 Patent) (Compl. ¶96, ¶134, ¶167). The complaint alleges that Defendant’s continued infringement after these dates constitutes willful infringement because Defendant knew or should have known of an unjustifiably high risk that its actions constituted infringement (Compl. ¶97, ¶135, ¶167).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of evidentiary sufficiency: Given that the internal architecture of the "AWS FPGA Shell" is proprietary and not publicly disclosed, can the plaintiff, through reverse engineering, discovery, and inferences from Defendant's own technical publications and patents, produce sufficient evidence to prove that the accused platform practices the specific hardware-based "reconfiguration," "interface," and "bandwidth apportionment" functions as required by the claims?
  • The case will also turn on a question of definitional scope: Can the claim term "prevents the reconfigurable logic region from directly accessing the physical interconnect" be construed to read on an architecture that provides a managed, high-performance interface (like DMA) through a hardware shell, or does the term require a more stringent form of physical or logical isolation that the accused platform does not provide?
  • A third key question will be one of functional implementation: Does the evidence show that the accused control and interface functions are "implemented in the reconfigurable logic region" of the FPGA itself, as required by Claim 1 of the ’934 patent, or are they performed by a combination of fixed-function hardware on the FPGA, the host CPU, and system software, potentially placing them outside the claim's scope?