DCT

1:23-cv-00822

Acqis LLC v. Sony Group Corporation

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00386, W.D. Tex., 04/14/2022
  • Venue Allegations: Plaintiff alleges venue is proper based on Defendant's regular and established places of business in the Western District of Texas, including an office in Austin and a data center, as well as the presence of employees and substantial sales within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s PlayStation video game consoles infringe five patents related to the use of Low Voltage Differential Signaling (LVDS) for high-speed serial data transfer in implementations of PCI Express and USB 3.x.
  • Technical Context: The patents concern foundational methods for converting parallel bus communications, like those of the traditional Peripheral Component Interconnect (PCI) standard, into high-speed, low-power serial data streams, a key technological shift that enabled modern computer interconnects.
  • Key Procedural History: The complaint states that the asserted patents are part of a portfolio that has been extensively litigated and licensed. Notably, it alleges that claims of each of the ACQIS Patents have been challenged in inter partes review (IPR) proceedings before the Patent Trial and Appeal Board (PTAB) and that the PTAB denied institution in each challenge, finding no reasonable likelihood that the challenged claims were invalid. The complaint also alleges that Plaintiff provided Defendant with actual notice of infringement on or around May 18, 2018, followed by meetings to discuss the matter.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date for all five patents-in-suit
2013-12-17 U.S. Patent No. RE44,654 issues
2014-09-16 U.S. Patent No. RE45,140 issues
2015-03-10 U.S. Patent No. 8,977,797 issues
2016-12-27 U.S. Patent No. 9,529,768 issues
2017-07-11 U.S. Patent No. 9,703,750 issues
2018-05-18 Defendant allegedly receives actual notice of infringement
2018-08-15 Plaintiff and Defendant meet for discussions
2018-09-26 Plaintiff and Defendant meet for a second discussion
2022-04-14 Complaint filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued December 27, 2016

The Invention Explained

  • Problem Addressed: The patent addresses the limitations of traditional parallel computer buses, such as the Peripheral Component Interconnect (PCI) bus, which require a large number of pins, are susceptible to noise, and are not "cable friendly," making them ill-suited for connecting system components over anything other than short, on-board distances (’797 Patent, col. 3:15-61).
  • The Patented Solution: The invention proposes replacing the high-pin-count parallel PCI bus with a low-pin-count, high-speed serial channel that uses Low Voltage Differential Signaling (LVDS). This channel serializes the address and data bits of a PCI transaction for transmission and then de-serializes them at the receiving end, preserving the transaction while enabling faster, more robust communication over longer distances or through cables (’768 Patent, col. 6:1-3; Abstract). This approach is designed to interface "PCI or PCI-like buses" using an LVDS channel (’768 Patent, col. 6:1-3).
  • Technical Importance: This technological approach of serializing parallel bus data for high-speed transmission was a critical step in the evolution of computer architecture, forming the basis for modern standards like PCI Express (PCIe) and high-speed USB. (Compl. ¶ 2).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶ 58).
  • Claim 1 of the ’768 Patent includes these essential elements:
    • A computer comprising an integrated central processing unit, interface controller, and Phase-Locked Loop (PLL) clock circuitry in a single chip.
    • A first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller.
    • The LVDS channel conveys address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form.
    • The LVDS channel comprises a first unidirectional, differential signal pair for a first direction and a second unidirectional, differential signal pair for a second, opposite direction.
    • The PLL clock circuitry generates different clock frequencies used to convey the PCI bus transactions through the LVDS channel.
  • The complaint reserves the right to assert additional claims. (Compl. ¶ 58).

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued July 11, 2017

The Invention Explained

  • Problem Addressed: This patent addresses the same technical problem as the ’768 patent: the physical and electrical limitations of parallel bus architectures in computer systems. (’797 Patent, col. 3:15-61).
  • The Patented Solution: The solution is also centered on using a bidirectional LVDS serial channel to carry the constituent parts of a PCI bus transaction between components like a CPU and a peripheral bridge. This patent's claims specifically add the conveyance of "byte enable information bits" as part of the serialized PCI transaction, which are signals used in the PCI standard to specify which byte lanes are active during a data transfer (’750 Patent, Claim 1).
  • Technical Importance: The inclusion of byte enable information ensures that the serialized transaction maintains the full functionality of the original parallel PCI bus transaction, which is critical for compatibility and proper operation of connected devices. (Compl. ¶ 96).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶ 86).
  • Claim 1 of the ’750 Patent includes these essential elements:
    • A computer comprising an integrated central processing unit and interface controller in a single chip.
    • A system memory directly coupled to the integrated CPU and interface controller.
    • A first LVDS channel directly extending from the interface controller that conveys address bits, data bits, and byte enable information of a PCI bus transaction in a serial bit stream.
    • The LVDS channel comprises a first unidirectional, differential signal pair for a first direction and a second unidirectional, differential signal pair for a second, opposite direction.
  • The complaint reserves the right to assert additional claims. (Compl. ¶ 86).

Multi-Patent Capsule: U.S. Patent No. 8,977,797

  • Patent Identification: U.S. Patent No. 8,977,797, "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel," issued March 10, 2015.
  • Technology Synopsis: This patent claims a method for improving data communication by connecting a CPU directly to an LVDS channel. The method involves increasing data throughput by using multiple pairs of differential signal lines and conveying encoded address and data bits of a PCI bus transaction over the serial channels. (’797 Patent, Abstract; Claim 14).
  • Asserted Claims: Independent claim 14. (Compl. ¶ 111).
  • Accused Features: The manufacturing and testing of Sony's PlayStation consoles, which allegedly utilize a multi-lane PCIe interface to connect the CPU to a southbridge and other peripherals. (Compl. ¶¶ 116-124).

Multi-Patent Capsule: U.S. Patent No. RE44,654

  • Patent Identification: U.S. Patent No. RE44,654, "Data Security Method and Device for Computer Modules," issued December 17, 2013.
  • Technology Synopsis: This patent claims a method of increasing a computer's external data communication speed. The method involves connecting a first LVDS channel to an integrated CPU and graphics controller and a second LVDS channel to a connector for an external console, with each channel comprising bidirectional serial channels and enabling the conveyance of different protocols (e.g., PCI and USB). (’654 Patent, Claim 20).
  • Asserted Claims: Independent claim 20. (Compl. ¶ 138).
  • Accused Features: The manufacture of PlayStation consoles, which allegedly use a first LVDS channel (PCIe) for internal components and a second LVDS channel (USB 3.x) for external ports, thereby enabling USB protocol data to be conveyed. (Compl. ¶¶ 143, 147-150).

Multi-Patent Capsule: U.S. Patent No. RE45,140

  • Patent Identification: U.S. Patent No. RE45,140, "Data Security Method and Device for Computer Modules," issued September 16, 2014.
  • Technology Synopsis: This patent claims a method of improving computer performance by obtaining an integrated CPU/graphics controller and connecting it to multiple differential signal channels. These channels are used for internal communication (a first LVDS channel) and external communication (a second LVDS channel and a separate differential signal channel for video output like HDMI). (’140 Patent, Claim 35).
  • Asserted Claims: Independent claim 35. (Compl. ¶ 164).
  • Accused Features: The manufacture of PlayStation consoles, which allegedly integrate a CPU/GPU and connect it to a PCIe interface (first LVDS channel), an HDMI port (differential signal channel), and USB ports (second LVDS channel). (Compl. ¶¶ 169-177).

III. The Accused Instrumentality

Product Identification

  • The Accused Instrumentalities are Sony's video game consoles, with the PlayStation 4 series (including the PlayStation 4, PlayStation 4 Slim, and PlayStation 4 Pro models) identified as exemplary infringing products. (Compl. ¶¶ 40, 43, 59).

Functionality and Market Context

  • The complaint alleges that the accused consoles are computer systems that contain an integrated central processing unit (CPU) and graphics processing unit (GPU) on a single processor chip, identified as the Sony CXD90059GB. (Compl. ¶¶ 62-63). This processor is connected to a southbridge chip (Sony CXD90042GG) via an on-chip four-lane (x4) PCI Express (PCIe) interface. (Compl. ¶ 67). The complaint provides a teardown photograph showing the processor on the console's motherboard. (Compl. p. 17, "Teardown photograph of CXD90059GB processor from PlayStation 4 Slim."). The consoles also provide external SuperSpeed USB (USB 3.x) ports for connecting peripherals. (Compl. ¶ 146). The complaint asserts that Sony's sales of PlayStation gaming hardware generated approximately $4.96 billion in global revenue in 2020. (Compl. ¶ 37).

IV. Analysis of Infringement Allegations

’768 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A computer comprising an integrated central processing unit, interface controller and Phase-Locked Loop (PLL) clock circuitry in a single chip The PlayStation 4 Slim console contains a single processor chip (Sony CXD90059GB) that integrates an octa-core CPU, a GPU, and an interface controller for PCIe, which includes a Physical Layer (PHY) containing PLL clock circuitry. ¶62-65 col. 22:2-5
a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller The processor's on-chip PCIe interface controller provides a direct connection to a four-lane PCIe physical interface, which functions as the claimed LVDS channel. ¶66-67 col. 22:6-7
that conveys address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form The PCIe interface transmits Transaction Layer Packets (TLPs) that contain both address and data information, thereby conveying the address and data bits of a bus transaction in a serial stream. ¶68, 70 col. 21:58-61
wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction Each lane of the PCIe interface contains a transmit (Tx) differential pair for sending data in one direction and a receive (Rx) differential pair for sending data in the opposite direction, enabling simultaneous bidirectional communication. A diagram illustrates this Tx/Rx pair structure for each PCIe lane. (Compl. p. 20, "PCI Express Links and Lanes"). ¶69 col. 22:8-13
and wherein the PLL clock circuitry generates different clock frequencies, which are used to convey the PCI bus transactions through the LVDS channel The PLL clock circuitry within the processor's PCIe PHY generates multiple clock frequencies, including a high-speed bitrate clock (e.g., 2.5 GHz or higher) for serial transmission and a lower-speed interface clock (e.g., 125/250 MHz) for the parallel interface to the controller logic. ¶71-72 col. 22:14-17

Identified Points of Contention:

  • Scope Questions: A primary question will be whether the term "Peripheral Component Interconnect (PCI) bus transaction" can be construed to read on the packet-based transactions of the accused PCI Express (PCIe) standard. The complaint suggests the patent covers "PCI or PCI-like buses," which may support a broader interpretation. (Compl. ¶ 42).
  • Technical Questions: The analysis may focus on whether the specific electrical characteristics of the PCIe physical layer meet the definition of a "Low Voltage Differential Signal (LVDS) channel" as understood in the patent. The complaint alleges this based on the fundamental nature of high-speed serial interconnects. (Compl. ¶ 68). Another question is whether the generation of a bitrate clock and an interface clock within the PCIe PHY constitutes generating "different clock frequencies" for the purpose of conveying the transaction, as claimed.

’750 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A computer comprising an integrated central processing unit and interface controller in a single chip The PlayStation 4 Slim console’s Sony CXD90059GB processor integrates a CPU and a PCIe interface controller on one chip. A teardown photograph of this processor is provided as evidence. (Compl. p. 39, "Teardown photograph of the PlayStation 4 Slim showing the CPU mounted on a standard motherboard."). ¶90 col. 6:21-23
a system memory directly coupled to the integrated central processing unit and interface controller The PlayStation 4 Slim contains 8 GB of GDDR5 DRAM which is directly coupled to the processor chip, which contains a memory controller. ¶97 col. 6:24-26
a first LVDS channel directly extending from the interface controller that conveys address bits, data bits, and byte enable information of a PCI bus transaction in a serial bit stream The processor's PCIe interface transmits Transaction Layer Packets (TLPs) containing address, data, and byte enable ("BE") information bits (e.g., "Last DW BE," "1st DW BE") in a serial stream. The complaint includes an annotated diagram of a PCIe request header to show these BE fields. (Compl. p. 34, "64-bit Address Memory Request Header"). ¶94, 96 col. 6:27-32
wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction Each lane of the PCIe interface utilizes separate unidirectional differential pairs for transmitting and receiving data, allowing for simultaneous bidirectional data flow. ¶95 col. 6:33-37

Identified Points of Contention:

  • Scope Questions: As with the ’768 patent, the construction of "PCI bus transaction" to cover PCIe will be central. Additionally, the dispute may turn on whether the "First DW BE" and "Last DW BE" fields within a PCIe TLP header (Compl. p. 34) constitute "byte enable information bits of a PCI bus transaction" as contemplated by the patent.
  • Technical Questions: A key question will be how the system memory is "directly coupled" to the integrated CPU and interface controller. The complaint alleges this is accomplished via an integrated memory controller on the processor chip. (Compl. ¶ 97).

V. Key Claim Terms for Construction

  • The Term: "Peripheral Component Interconnect (PCI) bus transaction"

    • Context and Importance: This term is the core of the asserted claims. Its interpretation will determine whether the patents, which explicitly reference the legacy PCI standard, are applicable to the accused products, which use the successor PCI Express (PCIe) standard. Practitioners may focus on this term because the technical protocols for PCI (a parallel, shared bus) and PCIe (a point-to-point, packet-based serial bus) are substantially different.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification of the related ’768 patent states the invention "advantageously use[] an LVDS channel for the hereto unused purpose of interfacing PCI or PCI-like buses." (’768 Patent, col. 6:1-3). This language suggests the inventor contemplated application beyond the strict confines of the legacy PCI standard existing at the time.
      • Evidence for a Narrower Interpretation: The detailed description in the parent ’797 patent extensively references specific PCI signals by name (e.g., FRAME#, IRDY#, TRDY#, DEVSEL#) and describes their function within a traditional PCI protocol. (’797 Patent, FIG. 16; col. 21:1-67). This could support a narrower construction limited to transactions that use these specific signals.

  • The Term: "Low Voltage Differential Signal (LVDS) channel"

    • Context and Importance: This term defines the physical communication medium. The infringement case hinges on the accused PCIe interface qualifying as an "LVDS channel."
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes an LVDS channel functionally as being "more cable friendly, faster, consumes less power, and generates less noise" than a parallel PCI channel. (’797 Patent, col. 4:1-4). This functional description, focusing on the benefits of low voltage and differential signaling, could be argued to encompass the PCIe physical layer, which shares these characteristics.
      • Evidence for a Narrower Interpretation: The patent may be interpreted in light of specific LVDS standards that were prevalent at the time of invention (circa 1999). If the PCIe physical layer operates according to a different electrical standard, a defendant may argue it does not meet this limitation.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement under 35 U.S.C. § 271(b). It asserts that Sony sells the Accused Instrumentalities to customers and provides instructions (e.g., user manuals) that direct end users to power on and use the consoles in their normal, intended manner, which allegedly causes direct infringement of the patents. (Compl. ¶¶ 51, 78, 103).
  • Willful Infringement: The complaint alleges willful infringement based on pre-suit knowledge. It states that Sony received actual notice of the patents and the infringement allegations on or around May 18, 2018, and subsequently "chose not to cease infringement" and "remained willfully blind," thus rendering its continued infringement deliberate and egregious. (Compl. ¶¶ 43, 46, 81).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "Peripheral Component Interconnect (PCI) bus transaction," which is rooted in the technical context of the parallel PCI standard of the late 1990s, be construed to cover the serialized, packet-based communications of the modern PCI Express (PCIe) standard implemented in the accused consoles?
  • A key evidentiary question will be one of technical implementation: assuming the patents cover PCIe, what evidence will demonstrate that the specific integrated circuits within Sony's consoles—such as the processor's on-chip interface controller and PLL clock circuitry—operate in a manner that satisfies the detailed structural and functional limitations of the asserted claims?
  • A central legal question, particularly for damages, will be one of timing and knowledge: given the allegation that Sony had actual notice of infringement as of May 2018, the case will likely examine the extent of Sony's actions after that date to determine whether any ongoing infringement was willful.