DCT

1:23-cv-00899

Professor Masahiro Iida v. Intel Corporation

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00662, W.D. Tex., 06/24/2022
  • Venue Allegations: Venue is alleged to be proper in the Western District of Texas because Intel maintains multiple regular and established places of business in the district, including research and development facilities in Austin.
  • Core Dispute: Plaintiff alleges that Defendant’s Field Programmable Gate Array (FPGA) and System-on-Chip (SoC) products, which incorporate Adaptive Logic Modules (ALMs), infringe a patent related to reconfigurable look-up table architecture.
  • Technical Context: The technology concerns the fundamental building blocks of FPGAs—programmable chips that can be configured by a customer after manufacturing—and specifically addresses methods for improving their logic density and efficiency.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of the patent and its infringement claims via a letter to Intel’s General Counsel on February 19, 2018. The patent-in-suit expired on June 28, 2022, four days after the complaint was filed, focusing the dispute entirely on past damages.

Case Timeline

Date Event
2001-06-29 ’737 Patent Priority Date
2002-06-28 ’737 Patent U.S. Filing Date
2004 First Accused Product Line Launch (Stratix II)
2004-11-02 ’737 Patent Issue Date
2015-12-28 Intel acquires Altera Corporation
2018-02-19 Pre-suit notice letter sent to Intel
2022-06-24 Complaint Filing Date
2022-06-28 ’737 Patent Expiration Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,812,737 - "PROGRAMMABLE LOGIC CIRCUIT DEVICE HAVING LOOK UP TABLE ENABLING TO REDUCE IMPLEMENTATION AREA," issued November 2, 2004

The Invention Explained

  • Problem Addressed: The patent’s background section describes a problem in conventional FPGAs where Look-Up Tables (LUTs), the core components for implementing logic, have a fixed input and output size. When a logic function smaller than the LUT's capacity is implemented, the assigned LUT is underutilized, leading to an "unnecessary increase of implementation area (logic and routing circuitry area; circuit area)" and wasted silicon resources (’737 Patent, col. 1:59-63).
  • The Patented Solution: The invention proposes a flexible LUT architecture that can be reconfigured to operate in different modes. The patented LUT is built from a "plurality of LUT units" and is governed by an "internal configuration control circuit" (’737 Patent, Abstract). This control circuit allows the single, larger LUT to function either as one large logic unit or be "fractured" into multiple, smaller, independent LUTs, thereby matching the hardware resources more efficiently to the specific logic function required (’737 Patent, col. 2:4-8; Fig. 6).
  • Technical Importance: This approach to creating adaptable logic blocks enables higher logic density and more efficient power consumption in FPGAs, which are key metrics for semiconductor performance (Compl. ¶31).

Key Claims at a Glance

  • The complaint asserts infringement of at least independent Claim 1 (Compl. ¶56). The right to assert other claims may be reserved.
  • The essential elements of Claim 1 are:
    • A look up table of M inputs and N outputs, comprising:
    • a plurality of LUT units;
    • and an internal configuration control circuit controlling an internal configuration of said plurality of LUT units, wherein said internal configuration control circuit comprises
    • a plurality of selectors selecting I/O signals of said plurality of LUT units, and
    • a selector control circuit having a memory, controlling said plurality of selectors in accordance with data stored in said memory, and defining the internal configuration of said plurality of LUT units.

III. The Accused Instrumentality

Product Identification

  • The accused products are Intel's programmable logic devices (FPGA and SoC chips) that employ Adaptive Logic Modules (ALMs) (Compl. ¶39). The complaint lists numerous product families, including Stratix, Arria, Cyclone, and Agilex, that allegedly incorporate the infringing ALM technology (Compl. ¶44).

Functionality and Market Context

  • The complaint alleges that ALMs are the fundamental logic blocks in the accused Intel FPGAs (Compl. ¶60). It asserts that these ALMs feature a flexible architecture that allows them to be configured in various modes, such as implementing two independent 4-input LUTs or a single 6-input LUT within one module (Compl. ¶65, p. 14, Table 1). The complaint includes a table from an Altera white paper to illustrate the various combinational logic configurations supported by an ALM (Compl. p. 14, Table 1). The complaint alleges that sales of the accused products have generated at least $11.5 billion in revenue for Intel over the six years preceding the filing of the suit (Compl. ¶54).

IV. Analysis of Infringement Allegations

’737 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A look up table of M inputs and N outputs, comprising: Intel's ALMs contain look up tables (LUTs) that have a specified number of inputs and outputs. An ALM block diagram is provided showing these I/O connections (Compl. p. 12, Fig. 6). ¶62 col. 2:4-5
a plurality of LUT units; The LUTs within Intel's ALMs are alleged to be composed of multiple LUT units. The complaint presents a diagram highlighting these constituent units within the larger ALM structure (Compl. p. 13, Fig. 6). ¶63 col. 2:5-6
and an internal configuration control circuit controlling an internal configuration of said plurality of LUT units... The ALMs are alleged to contain an internal configuration control circuit that manages the internal arrangement of the LUT units. This allows the ALM to support different logic configurations, as detailed in a provided flexibility table (Compl. p. 14, Table 1). ¶64-65 col. 2:6-8
...wherein said internal configuration control circuit comprises a plurality of selectors selecting I/O signals of said plurality of LUT units... The ALM's internal control circuit is alleged to include multiple selectors that route the input/output signals for the LUT units. The complaint provides a diagram from an Altera document highlighting these selectors (Compl. p. 15, Fig. 6). ¶66 col. 2:21-23
...and a selector control circuit having a memory, controlling said plurality of selectors in accordance with data stored in said memory, and defining the internal configuration of said plurality of LUT units. The ALM's control circuit is alleged to include a selector control circuit with a memory, which uses stored data to control the selectors and thereby define the ALM's configuration. The complaint cites a technical paper to support this allegation (Compl. p. 15, Fig. 9). ¶67 col. 2:23-28

Identified Points of Contention

  • Scope Questions: A potential issue is whether the term "internal configuration control circuit" as described in the ’737 Patent reads on the specific circuitry within Intel's ALMs. Intel may argue that its ALM architecture, developed by Altera, implements configuration control in a manner materially different from the specific embodiments disclosed in the patent, such as the "mode changing memory 71" that stores user-designated data (’737 Patent, Fig. 6, col. 5:29-31).
  • Technical Questions: The complaint relies on public-facing documents, including an Altera white paper and a third-party technical article, to evidence the internal workings of the ALMs (Compl. ¶62, ¶67). A key question for the court will be whether the functional descriptions in these documents are sufficient and accurate representations of the accused products' operation, and whether that operation meets the specific limitations of Claim 1, particularly the "selector control circuit having a memory."

V. Key Claim Terms for Construction

  • The Term: "internal configuration control circuit"

    • Context and Importance: This term is central to the claimed invention, as it performs the function of enabling the LUT's flexible, multi-mode operation. The scope of this term will likely be a primary focus of the dispute, determining whether the control logic within Intel's ALM falls within the patent's claims.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent abstract and claims describe the circuit in broad, functional terms as "controlling an internal configuration of the plurality of LUT units" (’737 Patent, Abstract; col. 10:52-55). Plaintiff may argue this language covers any circuit that achieves this re-configurability.
      • Evidence for a Narrower Interpretation: The specification discloses a specific embodiment where control is implemented via a "mode changing memory 71" storing "3 bits data X, Y, Z designated by a user" which drives various selectors (’737 Patent, col. 5:26-44; Fig. 6). Defendant may argue the claim term should be limited to an architecture that relies on such a stored, user-defined mode-setting mechanism.

  • The Term: "selector control circuit having a memory"

    • Context and Importance: This limitation defines a key sub-component of the broader control circuit. Its construction will be critical, as it requires a specific combination of a "memory" and a "selector control circuit" that uses the memory's contents.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification states this circuit "may comprise a memory" that controls selectors "in accordance with data stored in the memory" (’737 Patent, col. 2:25-28). The use of "may" and the general functional language could support a construction that is not limited to a single type of memory or control logic.
      • Evidence for a Narrower Interpretation: The detailed description shows the memory (71) and selectors (e.g., 721, 722) as distinct components operating based on pre-defined selection signals "F0" and "F1" derived from the memory's stored data (’737 Patent, col. 5:35-44). Defendant may argue that this structure implies a requirement for a static, programmable memory element separate from the selector logic itself, and not, for example, configuration data that is part of a dynamic bitstream.

VI. Other Allegations

Indirect Infringement

  • Plaintiff alleges induced infringement, asserting that Intel knowingly encouraged infringement by its distributors and end customers. The alleged inducing acts include providing the accused products, along with "information and instructions... on the use of the Accused Products" and other sales support (Compl. ¶80, ¶82).

Willful Infringement

  • The complaint alleges willful infringement based on Intel having received "actual notice of the '737 patent, and of Professor Iida's specific claims" via a certified letter sent on February 19, 2018 (Compl. ¶69-70). Plaintiff alleges that despite this notice, Intel "persisted in making, using, offering to sell, and selling the Accused Products," making its infringement "deliberate and intentional" (Compl. ¶71-72).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of claim construction and technical mapping: Can the specific architectural elements of the ’737 patent’s claims, particularly the "internal configuration control circuit" and its "selector control circuit having a memory," be construed to read on the functionality of Intel's ALMs, which were independently developed by Altera? The case may turn on whether the functional similarities alleged in the complaint withstand scrutiny against the detailed implementation of both the patented invention and the accused devices.
  • As the patent has expired, the case is exclusively about past damages. A key question will therefore be the impact of the February 2018 notice letter. This date provides a clear line for alleged willful infringement, potentially exposing Intel to enhanced damages for over four years of sales of its allegedly infringing products. The dispute will likely focus heavily on evidence of willfulness post-notice and the resulting damages calculation.