Polaris PowerLED Tech LLC v. Western Digital Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Polaris PowerLED Technologies, LLC (California)
  • Defendant: Western Digital Corporation and Western Digital Technologies, Inc. (Delaware)
  • Plaintiff’s Counsel: The Dacus Firm, P.C.; Kramer Alberti Lim & Tonkovich LLP
• Case Identification: 1:24-cv-00101, W.D. Tex., 01/30/2024
• Venue Allegations: Plaintiff alleges that venue is proper in the Western District of Texas because Defendants maintain a regular and established place of business in Austin and have committed acts of infringement in the District. The complaint further alleges that the two defendant entities operate as an integrated organization, attributing the actions of one to the other for venue purposes.
• Core Dispute: Plaintiff alleges that Defendant’s solid-state drive (SSD) products infringe three patents related to nonvolatile memory controller interrupt management, adaptive error correction coding schemes, and distributed parity data generation.
• Technical Context: The technology at issue involves flash memory controllers for SSDs, which are foundational components for high-speed data storage in consumer, enterprise, and data center applications.
• Key Procedural History: The complaint alleges that Defendant Western Digital was aware of the ’968 Patent prior to the lawsuit because it was cited as prior art during the prosecution of at least five U.S. patents assigned to Western Digital. Plaintiff also alleges sending a notice letter to Defendants on January 23, 2024, seven days before filing the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,554,968 - “Interrupt Technique for a Nonvolatile Memory Controller”

• Issued: October 8, 2013. (Compl. ¶24).

The Invention Explained

• Problem Addressed: In systems using the Nonvolatile Memory Express (NVMe) interface, a host computer must communicate with a non-volatile memory subsystem. A technical challenge is for the host computer to efficiently determine when a memory command has been completed by the subsystem without expending excessive processing resources to constantly monitor for a completion status. (’968 Patent, col. 2:49-54).
• The Patented Solution: The patent describes a nonvolatile memory controller containing an "interrupt manager." After the controller processes a command, it places a completion status into a "completion queue" in the host's memory. The interrupt manager is configured to monitor the state of this queue and, upon detecting an unprocessed completion status, generate and transmit an "interrupt message packet" to the host. This alerts the host to the completed task, obviating the need for the host to continuously poll the queue. (’968 Patent, Abstract; col. 2:36-44).
• Technical Importance: This interrupt-based notification system is designed to reduce the computational overhead on the host processing unit, a critical factor for maintaining high performance in modern storage systems. (Compl. ¶27).

Key Claims at a Glance

• The complaint asserts at least independent claim 1. (Compl. ¶31).
• Essential elements of Claim 1 include:
  • A nonvolatile memory controller for alerting a host processing unit to an unprocessed completion status.
  • An interrupt manager configured to:
    • generate a completion queue state indicating a completion queue event;
    • generate an interrupt vector state based on the completion queue state;
    • determine, based on the interrupt vector state, that the completion queue contains an unprocessed completion status; and
    • generate an interrupt message packet to trigger an interrupt in the host.
  • The completion queue state includes a "doorbell update status" indicating the host has updated a head pointer stored in the controller.

U.S. Patent No. 9,183,085 - “Systems and Methods for Adaptively Selecting from among a Plurality of Error Correction Coding Schemes in a Flash Drive for Robustness and Low Latency”

• Issued: November 10, 2015. (Compl. ¶25).

The Invention Explained

• Problem Addressed: Multi-level cell (MLC) flash memory is less expensive than single-level cell (SLC) flash but degrades more quickly and is more prone to errors. Conventional, static error correction coding (ECC) methods can be inefficient for achieving the very low uncorrectable bit error rates required for enterprise storage applications while maximizing the device's lifespan and performance. (’085 Patent, col. 1:22-2:4).
• The Patented Solution: The invention proposes a method of adaptively selecting an ECC scheme. The system determines the current bit error rate (BER) for a given region of memory. This BER is then compared against predefined thresholds that correspond to a set of "predefined gears." Each gear represents a different ECC scheme with a unique balance between data payload size and error correction strength. Based on the comparison, the system selects the appropriate gear, applying stronger (and more performance-intensive) error correction only when the memory has degraded enough to require it. (’085 Patent, Abstract; col. 2:5-24).
• Technical Importance: This adaptive ECC technology enables the use of denser, more cost-effective MLC or TLC flash memory in high-reliability applications by dynamically adjusting the error correction strength to match the health of the memory, thereby optimizing performance and extending the drive's operational life. (Compl. ¶28).

Key Claims at a Glance

• The complaint asserts at least independent claim 1. (Compl. ¶50).
• Essential elements of Claim 1 include:
  • A method of selecting an error correction coding (ECC) scheme.
  • Determining a bit error rate (BER) associated with a region of two or more flash memory pages that can be read simultaneously.
  • Comparing the BER to thresholds corresponding to a set of "predefined gears" (e.g., a first gear and a second gear).
  • The predefined gears correspond to different ECC schemes, where the first gear has a different data payload size and correction capability than the second gear.
  • The memory space for data payload varies between gears to accommodate a varying number of parity symbols.
  • Selecting a gear for the region based on the comparisons.
  • The determining, comparing, and selecting steps are performed by an integrated circuit.

U.S. Patent No. 8,601,346 - “System and Method for Generating Parity Data in a Nonvolatile Memory Controller by Using a Distributed Processing Technique”

• Issued: December 3, 2013. (Compl. ¶26).

Technology Synopsis

The patent addresses the computational burden of generating parity data for RAID (redundant array of independent disks) operations. (’346 Patent, col. 1:18-30). The described solution utilizes a distributed architecture within the memory controller, comprising multiple "command processing units" that handle data write commands in parallel and a separate "parity calculator." This calculator generates the parity block "on the fly" as it receives the sequence of data blocks, which avoids the need to buffer all data blocks simultaneously and thereby reduces power consumption and the required silicon area. (’346 Patent, Abstract; col. 2:1-17).

Asserted Claims

Independent claim 1. (Compl. ¶70).

Accused Features

The accused SSDs are alleged to contain controllers with multiple processing units (e.g., ARM cores) that process data update commands and a parity calculator that supports RAID-like XOR-based schemes to perform data stripe operations. (Compl. ¶¶73, 76, 78).

III. The Accused Instrumentality

Product Identification

The accused products are Defendants' solid-state drives (SSDs) that support the NVMe standard, including but not limited to the WD Black, Blue, Green, Red, Gold, and Ultrastar product lines. (Compl. ¶¶3, 33). The complaint presents a product brief for the "WD_BLACK SN770 NVMe SSD" as an exemplary accused product. (Compl. ¶33).

Functionality and Market Context

The accused products are high-performance storage devices that use the NVMe communications protocol over a PCIe interface to connect to a host computer. (Compl. ¶¶33-34). The complaint alleges these SSDs incorporate controllers with specific functionalities, including an interrupt management system compliant with the NVMe standard, a "multi-gear" Low-Density Parity-Check (LDPC) error correction engine, and support for RAID-like data striping operations. (Compl. ¶¶36, 52, 76). These products are marketed for a wide range of applications, from consumer gaming PCs to enterprise data centers. (Compl. ¶33).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,554,968 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central question may be whether the claimed "interrupt manager" describes a specific structure and method distinct from the standard operation of any NVMe-compliant controller. The complaint’s allegations rely heavily on mapping elements of the public NVMe specification to claim terms, which raises the question of whether the patent claims an inventive concept beyond the industry standard itself.
  • Technical Questions: Claim 1 requires the controller's "interrupt manager" to determine that the queue contains an unprocessed status based on the interrupt vector state. The complaint alleges infringement by pointing to the controller generating an interrupt to signal a new entry. What evidence suggests this determination is made by the controller in the specific manner claimed, as opposed to the host being responsible for processing the queue and notifying the controller via a doorbell register after the fact?

U.S. Patent No. 9,183,085 Infringement Allegations

• Identified Points of Contention:
  • Technical Questions: The claim requires determining a BER for a "region" whose pages "can be read simultaneously." The complaint points to multi-plane reads as evidence of simultaneous reading. A key technical question will be whether the BER is determined for the same "region" that is subject to these simultaneous reads, as required by the claim's plain language.
  • Scope Questions: Does the term "gear" as used in Defendant's marketing and technical documents map to the specific definition in Claim 1, which requires a variation in "data payload size"? A defendant may argue that its "multi-gear" system refers to different decoding algorithms or power modes applied to a fixed data/parity structure, not the dynamic reallocation of memory space between payload and parity symbols as claimed.

V. Key Claim Terms for Construction

’968 Patent

• The Term: "interrupt manager"
• Context and Importance: This term defines the central component of Claim 1. The infringement analysis depends entirely on whether the accused NVMe controller contains a structure that meets the definition of an "interrupt manager" and performs all its recited functions.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not provide a specific glossary definition, which may support an argument that the term should be given its plain and ordinary meaning to one of skill in the art—a logical or physical unit that manages interrupt generation and handling.
  • Evidence for a Narrower Interpretation: The specification discloses a specific embodiment of the "interrupt manager 1040" that includes an "interrupt manager controller 1100," a "completion queue state memory 1105," and an "interrupt vector state memory 1110." (’968 Patent, FIG. 11). A defendant may argue that the term is not generic but is implicitly defined by this more complex, disclosed structure.

’085 Patent

• The Term: "gear"
• Context and Importance: Plaintiff's infringement theory relies on mapping Defendant's publicly described "multi-gear architecture" to the claimed "gears." The construction of this term is therefore critical to determining whether the accused products practice the claimed invention.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent states that "predefined gears correspond to different predefined ECC schemes." (’085 Patent, col. 32:9-10). This language could support a construction where any system that adaptively switches between different types of ECC qualifies.
  • Evidence for a Narrower Interpretation: Claim 1 explicitly requires that "the first gear has a different data payload size and correction capability than the second gear" and that "the amount of memory space allocated for the storage of data payload...varies between the first gear and the second gear." (’085 Patent, col. 32:11-22). This language strongly suggests that a "gear" must involve this specific trade-off between user data capacity and error correction overhead, not merely a switch between different decoding algorithms.

VI. Other Allegations

• Indirect Infringement: For all three patents, Plaintiff alleges induced infringement based on Defendants' instructions to customers through user guides, support information, videos, and marketing materials that encourage use of the accused SSDs. (Compl. ¶¶42-43, 63-64, 86-87). Contributory infringement is also alleged, asserting the accused SSDs are material components for practicing the patents and are not staple articles of commerce suitable for substantial non-infringing use. (Compl. ¶¶46, 65, 88).
• Willful Infringement: Willfulness allegations are based on both pre-suit and post-suit knowledge. Pre-suit knowledge of the ’968 Patent is alleged because Defendant cited the patent as prior art in its own patent applications. (Compl. ¶44). For all asserted patents, willfulness is alleged based on a notice letter sent by Plaintiff on January 23, 2024, and on the filing of the complaint itself. (Compl. ¶¶45, 62, 85).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: does the claimed "interrupt manager" of the ’968 Patent describe a specific architecture and logic flow that is distinct from the standard, publicly-defined operation of any NVMe-compliant controller, or does the claim effectively read on the industry standard itself?
• A key evidentiary question will be one of functional equivalence: does Western Digital's "multi-gear" ECC architecture, as described in its technical and marketing documents, perform the specific function required by Claim 1 of the ’085 Patent—dynamically varying the "data payload size" to trade storage capacity for error correction strength—or does it represent a functionally distinct, non-infringing alternative, such as switching between different decoding algorithms while maintaining a fixed data-to-parity ratio?
• The dispute over the ’346 Patent will likely focus on a structural and operational analysis: can Plaintiff demonstrate that the accused multi-core controller and its RAID/XOR hardware map to the claimed structure of distinct "command processing units" and a "parity calculator" that generates parity "without storing each data block in a data buffer," a determination that will require a detailed examination of the controller's internal data paths and memory use.