DCT

1:24-cv-00218

InnoMemory LLC v. Regions Bank

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:24-cv-00218, W.D. Tex., 03/01/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant has an established place of business in the district, has committed acts of patent infringement in the district, and Plaintiff has suffered harm there.
  • Core Dispute: Plaintiff alleges that Defendant infringes patents related to power-saving techniques in random access memory (RAM) integrated circuits.
  • Technical Context: The patents relate to methods for reducing power consumption in semiconductor memory, a critical technology for both high-performance computing and battery-powered portable devices.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or relevant licensing history concerning the patents-in-suit.

Case Timeline

Date Event
1999-02-13 ’046 Patent Priority Date
2001-05-29 ’046 Patent Issue Date
2002-03-04 ’960 Patent Priority Date
2006-06-06 ’960 Patent Issue Date
2024-03-01 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle

The Invention Explained

  • Problem Addressed: The patent's background section describes a trade-off in prior art RAM design between performance and power consumption. Architectures that retrieve multiple data words per clock cycle are efficient for sequential "burst" reads but waste power during random reads where only one word is needed. Conversely, architectures that retrieve only one word per cycle conserve power on random reads but are less efficient for bursts. The patent identifies an "unfilled need for memory devices with low power consumption characteristics" ('046 Patent, col. 2:13-15).
  • The Patented Solution: The invention proposes a memory circuit that can operate in two different modes to optimize power usage. The circuit is capable of retrieving only a single data word from the memory array in one clock cycle for random read requests, thereby conserving power. For burst requests, the same circuit can retrieve more than one data word in a single clock cycle, preserving performance. A flip-flop is described as a mechanism to switch the memory between these two states ('046 Patent, col. 2:44-60).
  • Technical Importance: This flexible approach aims to provide lower average power consumption, a critical factor for portable computing systems and other power-sensitive electronics ('046 Patent, col. 2:11-13).

Key Claims at a Glance

  • The complaint asserts infringement of "exemplary method claims" without specifying them (Compl. ¶12). Independent claim 1 is a representative method claim.
  • Independent Claim 1:
    • A method of reading data from a memory array, comprising:
    • retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations; and
    • retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations.

U.S. Patent No. 7,057,960 - Method and architecture for reducing the power consumption for memory devices in refresh operations

The Invention Explained

  • Problem Addressed: The patent addresses high power consumption in DRAMs during standby mode. Conventional DRAMs must periodically refresh all memory cells to prevent data loss, even if only a small portion of the memory contains critical data. This process activates periphery array circuits for the entire memory array, which is inefficient and drains power, a particular problem for battery-powered devices ('960 Patent, col. 1:43-52). A noted disadvantage is that periphery circuits for all quadrants are activated even when less than the full array requires refreshing ('960 Patent, col. 2:25-28).
  • The Patented Solution: The invention describes a method for reducing power consumption by dividing the memory array into multiple "sections" (e.g., quadrants) and controlling background operations, such as refresh, on a per-section basis. By presenting control signals only to the periphery circuits of the section(s) that require refreshing, the circuits for other sections can remain inactive, thereby saving power. This selective activation is controlled via a programmable address signal ('960 Patent, col. 2:35-44; Fig. 3).
  • Technical Importance: This method allows for a "partial array refresh," significantly reducing standby power consumption, which is critical for extending the battery life of mobile devices ('960 Patent, col. 1:33-37).

Key Claims at a Glance

  • The complaint asserts infringement of "exemplary method claims" without specifying them (Compl. ¶18). Independent claim 1 is a representative method claim.
  • Independent Claim 1:
    • A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
    • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
    • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, methods, or services in its text. Instead, it states that "Exemplary Defendant Products" are identified in charts included as Exhibits 3 and 4 (Compl. ¶¶14, 20). These exhibits were not provided with the complaint.

Functionality and Market Context

The complaint does not provide any description of the accused products' technical functionality, features, or market positioning.

IV. Analysis of Infringement Allegations

The complaint incorporates infringement allegations by reference to claim chart exhibits that were not provided (Compl. ¶¶15, 21). The body of the complaint offers only conclusory allegations that the unspecified "Exemplary Defendant Products" practice the claimed technology and satisfy all claim elements (Compl. ¶¶14, 20). No specific facts mapping product features to claim limitations are included in the complaint itself.

No probative visual evidence provided in complaint.

  • Identified Points of Contention:
    • As the complaint lacks specific factual allegations, the central point of contention will be evidentiary: whether Plaintiff can produce evidence that Defendant’s accused instrumentalities practice the methods claimed in the ’046 and ’960 patents.
    • For the ’046 Patent, a key technical question may be one of operational modality. The analysis would focus on whether the accused products differentiate memory read operations based on the nature of the request, retrieving a single data word for random accesses while retrieving multiple data words for burst accesses, as required by the claim.
    • For the ’960 Patent, a core question may be one of architectural granularity. The dispute could center on whether the accused products possess a memory architecture with distinct "sections" whose background refresh operations can be independently controlled via programmable signals, as distinct from other known power-saving techniques.

V. Key Claim Terms for Construction

The complaint does not provide sufficient detail for analysis of claim construction disputes. However, based on the selected representative claims, certain terms may become central to the case.

  • Term: "bursts of related memory locations" (from ’046 Patent, Claim 1)
  • Context and Importance: This term defines one of the two distinct operational modes required by the claim. The scope of this term will be critical for determining whether a product’s pre-fetching, caching, or sequential access features fall within the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification discusses "burst read cycles (i.e., a number of sequential read operations...)" ('046 Patent, col. 2:67-3:3) and responding to "'continue the present burst' read requests" (col. 2:58-60), which could support construing the term to cover a wide range of sequential data accesses.
    • Evidence for a Narrower Interpretation: The abstract frames burst requests as "a first read request immediately followed by advance requests" ('046 Patent, Abstract). This language could support a narrower construction limited to accesses initiated by explicit burst or advance commands, rather than any incidental sequential read.
  • Term: "sections" (from ’960 Patent, Claim 1)
  • Context and Importance: The claim requires controlling background operations in a plurality of "sections." The definition of this term will determine whether an accused device's memory partitioning scheme (e.g., banks, sub-arrays) meets the architectural requirements of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The background of the invention uses the term "quadrants" when describing the problem in the prior art, and the summary of invention uses the more general term "sections," suggesting the latter is not limited to a four-part division ('960 Patent, col. 2:15-38). Dependent claim 3 explicitly recites "quadrants," which may imply the independent claim's use of "sections" is broader.
    • Evidence for a Narrower Interpretation: The figures and detailed description illustrate specific hardware configurations of sections with associated "periphery array circuits" ('960 Patent, Fig. 4). A defendant may argue that "sections" should be limited to partitions that have the specific, independently controllable peripheral circuitry disclosed in the patent's embodiments.

VI. Other Allegations

The complaint alleges only direct infringement (Compl. ¶¶12, 18). It contains no allegations to support indirect infringement or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

The analysis of this complaint reveals a case that, in its current state, will likely turn on the resolution of fundamental factual and definitional questions.

  • A primary issue will be evidentiary sufficiency: given the complaint's lack of specific factual allegations, a central question is whether Plaintiff can produce discovery evidence that maps the functionality of Defendant's accused products to the specific limitations of the asserted patent claims.
  • A key technical question for the ’046 Patent will be one of functional operation: does the accused technology implement a dual-mode read capability that distinguishes between "separate single unrelated memory locations" and "bursts of related memory locations" to modulate the number of data words retrieved per cycle?
  • A core architectural question for the ’960 Patent will be one of definitional scope: can the memory partitions within the accused products be properly characterized as "sections" with independently controllable background operations, as understood in the context of the patent, or do they operate on a different architectural principle?