InnoMemory LLC v. First United Bank

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: First United Bank (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 1:24-cv-00219, W.D. Tex., 03/01/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has an established place of business within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s use of certain unidentified products infringes patents related to random access memory architecture, performance, and power consumption.
• Technical Context: The patents-in-suit relate to fundamental methods for improving the efficiency of Dynamic Random-Access Memory (DRAM) by adapting data retrieval strategies to save power and by enabling partial-array refresh operations.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle"

The Invention Explained

• Problem Addressed: The patent describes a need for memory devices with lower power consumption, noting that prior art memories were inefficient because they were designed to retrieve either a single data word per clock cycle (optimal for random reads) or multiple data words (optimal for burst reads), but could not adapt between these modes to save power ('046 Patent, col. 2:1-15).
• The Patented Solution: The invention is a random access memory circuit that can operate in two different states. In a first state, it retrieves only one data word in a clock cycle, conserving power during random access operations. In a second state, it retrieves more than one data word in a single clock cycle, saving power during "burst read cycles." A flip-flop is used to switch between these states, allowing the memory to adapt its retrieval strategy to the type of read request ('046 Patent, Abstract; col. 2:45-56).
• Technical Importance: This adaptive approach to data retrieval was designed to provide significant power savings, a critical consideration for portable and other power-sensitive computing systems ('046 Patent, col. 2:12-15).

Key Claims at a Glance

The complaint asserts infringement of "one or more claims" without specifying which ones (Compl. ¶12). Independent claim 1 includes the following essential elements:

• A random access memory integrated circuit.
• A memory array capable of storing a plurality of data words.
• A data bus coupled to the memory array, having a width of more than one data word.
• The circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

The Invention Explained

• Problem Addressed: The patent notes that conventional Dynamic Random Access Memories (DRAMs) refresh all memory cells to maintain data integrity, even when the device is in a low-power standby mode where only a portion of the data needs to be retained. This full-array refresh consumes unnecessary power, which is detrimental for battery-powered devices ('960 Patent, col. 1:36-56).
• The Patented Solution: The invention provides a method and architecture for reducing power by controlling background operations, such as refresh, in different sections of the memory array independently. By activating the support circuits for only the sections being refreshed and leaving the circuits for other sections inactive, the system significantly reduces standby power consumption ('960 Patent, Abstract; col. 2:36-44).
• Technical Importance: This method enables "partial array refresh," a key feature for extending the battery life of mobile devices like portable telephones by minimizing power usage during standby periods ('960 Patent, col. 1:40-45).

Key Claims at a Glance

The complaint asserts infringement of "one or more claims" without specifying which ones (Compl. ¶18). Independent claim 1 recites a method with the following essential elements:

• A method for reducing power consumption during background operations in a memory array with a plurality of sections.
• Controlling the background operations in each section in response to one or more control signals.
• The background operations can be enabled simultaneously in two or more of the sections independently of any other section.
• Presenting the control signals and decoded address signals to one or more periphery array circuits of the sections.

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, models, or services. It refers to "Exemplary Defendant Products" that are purportedly identified in claim chart exhibits (Exhibits 3 and 4) which were not filed with the complaint (Compl. ¶¶12, 14, 18, 20).

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality or market context.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that Defendant directly infringes the patents-in-suit by "making, using, offering to sell, selling and/or importing" infringing products (Compl. ¶¶12, 18). The substantive infringement allegations are incorporated by reference from external exhibits (Exhibits 3 and 4) that were not included with the complaint (Compl. ¶¶15, 21). The complaint asserts narratively that the unidentified "Exemplary Defendant Products practice the technology claimed" by the patents and "satisfy all elements" of the asserted claims (Compl. ¶¶14, 20). Without the referenced exhibits, a detailed analysis of the infringement theory is not possible.

• Identified Points of Contention: Given that the defendant is a financial institution, not a technology manufacturer, a central issue may be its "use" of computer systems that allegedly contain infringing memory components.
  • Technical Questions for the '046 Patent: A potential factual dispute may center on whether the memory systems used by Defendant actually implement the claimed dual-mode read capability. The analysis may require evidence of how the memory controllers and DRAM modules in Defendant's systems respond to random versus burst read requests and whether this behavior maps to the specific state-based operation required by the claims.
  • Technical Questions for the '960 Patent: A key question may be whether the memory systems used by Defendant perform "partial array refresh" where sections are controlled "independently," as claimed. The analysis could turn on evidence of how refresh commands are issued and executed by the memory controllers in Defendant's systems, and whether these commands selectively activate periphery circuits for some memory sections while leaving others inactive.

V. Key Claim Terms for Construction

• The Term: "a data bus having a width of more than one data word" ('046 Patent, Claim 1).

• Context and Importance: This term is foundational to the claim, as the invention's power-saving capability derives from selectively retrieving either one word or multiple words from a bus that is physically capable of carrying more than one word at a time. The definitions of "data bus" and "data word" will be critical to determining the scope of the claim relative to modern memory architectures.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification provides an example of a "72-bit wide (double word) organization" from which "two 36-bit words can be retrieved," suggesting that a "word" can be a fraction of the total bus width ('046 Patent, col. 2:34-37). This may support a flexible definition not tied to a specific number of bits.
  • Evidence for a Narrower Interpretation: The detailed description focuses heavily on specific 36-bit and 72-bit wide embodiments. A party might argue that the term "data word" should be construed in light of these specific examples, potentially limiting the claim's applicability to other architectures.

• The Term: "controlling said background operations in each of said plurality of sections... independently" ('960 Patent, Claim 1).

• Context and Importance: This limitation appears to be the point of novelty. Infringement may depend on whether an accused system can control refresh operations in different memory sections separately and simultaneously, as opposed to issuing a global refresh command that affects all sections uniformly.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The abstract states the method involves "controlling the background operations in one or more sections" and presenting signals to "one or more periphery array circuits," which may support a construction where any non-global control of refresh meets the limitation ('960 Patent, Abstract).
  • Evidence for a Narrower Interpretation: The specification describes dividing a memory array into four "quadrants" and using specific control signals (REF0-REF3) to manage refresh for each quadrant (Compl. Ex. 2, FIG. 3; col. 4:11-16). A party could argue that "independently" requires a control architecture with distinct, programmable signals for each section, not merely a system that happens to have asynchronous refresh behavior.

VI. Other Allegations

• Willful Infringement: The complaint does not contain an explicit allegation of willful infringement. The prayer for relief requests that the case be declared "exceptional" under 35 U.S.C. § 285, but does not plead facts to support a claim of willfulness or seek enhanced damages under 35 U.S.C. § 284 for willful conduct (Compl. p. 5).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of evidence and specificity: given the complaint’s failure to identify any accused products or articulate a specific infringement theory, a primary question is what evidence Plaintiff will produce to show that the specific computer and memory systems used by Defendant, a financial institution, actually perform the patented methods for dual-mode data retrieval ('046 Patent) and independent partial-array refresh ('960 Patent).
• A key technical and legal question will be one of functional scope: does the operation of standardized, commodity DRAM and memory controllers found in general-purpose computer systems meet the specific architectural and control-method limitations of the patents-in-suit, or is there a fundamental mismatch between the patented inventions and how these widely used components actually function?