InnoMemory LLC v. Citigroup Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Citigroup Inc. (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 1:24-cv-00231, W.D. Tex., 03/04/2024
• Venue Allegations: Venue is asserted based on Defendant's established place of business in San Antonio, Texas.
• Core Dispute: Plaintiff alleges that Defendant infringes two patents related to power-saving techniques in random access memory (RAM) integrated circuits.
• Technical Context: The patents relate to methods for reducing power consumption in computer memory, a critical feature for performance and battery life in both server infrastructure and consumer electronics.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," Issued May 29, 2001

The Invention Explained

• Problem Addressed: The patent describes a need for memory devices with lower power consumption, particularly for portable computing systems. Prior art memory devices that retrieve multiple data words in every read cycle waste power when only one word is needed, as the unrequested words are simply discarded (’046 Patent, col. 2:3-15).
• The Patented Solution: The invention is a random access memory architecture that can operate in different modes to conserve power. It is capable of retrieving a single data word from its memory array in one clock cycle for random read requests, but can also retrieve more than one data word in a single clock cycle for "burst" requests (i.e., sequential read requests) (’046 Patent, Abstract). This dual-mode capability, controlled by internal circuitry, allows the memory to avoid accessing the power-intensive memory array on every clock cycle during a burst read, thereby saving power (’046 Patent, col. 3:7-20). The overall architecture is depicted in Figure 1, showing the memory array (102), decoders (104, 108), and control logic (112).
• Technical Importance: This approach allows memory performance to be tailored to the nature of the data request, conserving energy by minimizing unnecessary data retrieval from the core memory array.

Key Claims at a Glance

• The complaint states it asserts "one or more claims" and references exemplary method claims in an exhibit not provided with the complaint (Compl. ¶12). Independent claims 1 and 9 are representative of the patent's scope.
• Independent Claim 1 recites an apparatus, an integrated circuit, comprising:
  • A memory array capable of storing a plurality of data words.
  • A data bus coupled to the memory array with a width of more than one data word.
  • A flip-flop having a first state and a second state.
  • In the first state, the circuit retrieves one data word in a single clock cycle.
  • In the second state, the circuit retrieves more than one data word in the single clock cycle.
• Independent Claim 9 recites a method of reading data from a memory array, comprising the steps of:
  • Retrieving one data word from the memory array in a read clock cycle in response to a read request, if an advance control signal is not asserted.
  • Retrieving more than one data word from the memory array in the read clock cycle in response to the read request, if the advance control signal is asserted.
• The complaint does not explicitly reserve the right to assert dependent claims but alleges infringement of "one or more claims" (Compl. ¶12).

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations," Issued June 6, 2006

The Invention Explained

• Problem Addressed: The patent notes that many applications, such as battery-powered portable terminals, do not need to maintain data in all memory cells during standby or power-down modes. Conventional memory devices that refresh the entire memory array in such situations consume unnecessary power (’960 Patent, col. 1:40-52).
• The Patented Solution: The invention proposes a method and architecture for reducing power consumption by dividing the memory array into multiple sections (e.g., quadrants) and controlling background operations, such as memory refresh, independently for each section (’960 Patent, Abstract). By activating the periphery array circuits for only those sections containing data that must be retained, the device avoids the power consumption associated with refreshing the entire array (’960 Patent, col. 2:25-30). Figure 3 illustrates this concept, showing a refresh control block (134) that provides separate refresh-related signals (REF0-REF3) to different quadrants of the memory array (104).
• Technical Importance: This selective refresh capability allows for more granular power management in memory systems, which is critical for extending battery life in mobile devices.

Key Claims at a Glance

• The complaint states it asserts "one or more claims" and references exemplary method claims in an exhibit not provided with the complaint (Compl. ¶18). Independent claim 1 is representative of the patent's scope.
• Independent Claim 1 recites a method for reducing power consumption, comprising the steps of:
  • Controlling background operations in each of a plurality of sections of a memory array in response to one or more control signals.
  • The control signals are generated in response to a programmable address signal.
  • The background operations can be enabled simultaneously in two or more sections independently of any other section.
• The complaint does not explicitly reserve the right to assert dependent claims but alleges infringement of "one or more claims" (Compl. ¶18).

III. The Accused Instrumentality

• Product Identification: The complaint does not identify any specific accused products, methods, or services by name. It refers to "Exemplary Defendant Products" that are purportedly identified in claim charts attached as Exhibit 3 and Exhibit 4 (Compl. ¶¶12, 14, 18, 20).
• Functionality and Market Context: As Exhibits 3 and 4 were not attached to the publicly filed complaint, the complaint does not provide sufficient detail for analysis of the functionality or market context of the accused instrumentalities.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint's infringement allegations are made by incorporating by reference claim charts contained in Exhibit 3 (for the ’046 Patent) and Exhibit 4 (for the ’960 Patent) (Compl. ¶¶15, 21). As these exhibits were not provided, a claim-by-claim analysis of the infringement allegations is not possible based on the complaint document.

Identified Points of Contention

• Scope Questions: Based on the nature of the parties and the technology, a central issue may be whether the defendant, a financial services company that uses computer systems, can be a direct infringer of patents directed to the internal architecture and low-level operational methods of semiconductor memory components. The analysis for the ’046 Patent may raise the question of whether a system containing an "integrated circuit" satisfies a claim limitation directed to the circuit itself.
• Technical Questions: For the ’960 Patent, a key question may be what actions constitute "controlling said background operations" as recited in claim 1. The dispute may turn on whether this control is an automated, internal function of a memory component or an action attributable to the end-user of a system that contains such a component.

V. Key Claim Terms for Construction

The Term: "integrated circuit" (’046 Patent, Claim 1)

• Context and Importance: This term appears in an apparatus claim. Its construction will be critical to determining whether infringement can be attributed to the Defendant, which is an end-user of computer systems rather than a manufacturer of semiconductor components.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification frequently uses general terms such as "memory device" and "semiconductor memories" which could be argued to encompass systems incorporating such devices (’046 Patent, col. 1:21).
  • Evidence for a Narrower Interpretation: The patent's detailed description and figures are replete with specific circuit-level schematics (e.g., FIGs. 3, 7, 8) and discussions of transistor-level operations, which may support an interpretation limiting the term to a physical semiconductor chip (’046 Patent, col. 9:8–col. 13:40).

The Term: "controlling said background operations" (’960 Patent, Claim 1)

• Context and Importance: This term is central to the asserted method claim. The infringement analysis will depend on whether the actions of the Defendant, as a user of a larger system, can be considered to be "controlling" the low-level refresh operations within a memory component.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language requires control "in response to one or more control signals," which could arguably originate from higher-level system software or configurations managed by the user.
  • Evidence for a Narrower Interpretation: The patent's detailed description explains this control function with reference to specific internal circuits, such as the "Refresh Control" block (134) and "Array Control Circuit" (146), which receive command signals and generate low-level refresh signals (e.g., REF0-REF3) (’960 Patent, FIG. 3; col. 4:15-24). This suggests the "controlling" is an automated function performed by the memory device's own logic, not by the end-user.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain specific factual allegations to support claims of induced or contributory infringement. The headings for Counts 1 and 2 explicitly allege "Direct Infringement" (Compl. p. 3-4).
• Willful Infringement: The complaint does not allege pre- or post-suit knowledge of the patents by the Defendant to support a claim of willful infringement. The prayer for relief requests a declaration that the case is "exceptional" under 35 U.S.C. § 285, but the complaint body provides no factual basis for this request (Compl. ¶G.i).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central legal question will be one of attribution of infringement: can the act of using a system that contains memory components constitute direct infringement of claims directed to the internal architecture and low-level operational methods of those components? The dispute may focus on whether the actions of the Defendant, a financial services company, can be legally equated with the specific hardware-level functions described in the patents-in-suit.
• A key evidentiary question will be the factual basis for infringement: given that the complaint's technical infringement allegations are contained entirely within missing exhibits, a threshold issue for the case will be the undisclosed evidence purportedly showing that Defendant's unspecified systems practice the patented methods for power management in memory chips.