InnoMemory LLC v. Amarillo National Bank

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Amarillo National Bank (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 1:24-cv-00232, W.D. Tex., 03/04/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has an established place of business in the district.
• Core Dispute: Plaintiff alleges that Defendant’s use of certain products infringes two patents related to the architecture and operation of random access memory (RAM) circuits.
• Technical Context: The patents address methods for reducing power consumption in dynamic random access memory (DRAM) devices, a critical technology for both high-performance computing and portable electronic devices.
• Key Procedural History: The complaint does not reference any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," Issued May 29, 2001

The Invention Explained

• Problem Addressed: The patent’s background section describes the need for memory devices with low power consumption, particularly for portable computing systems. It notes an inefficiency in prior art memory architectures that are optimized for either single-word "random" reads or multi-word "burst" reads, but not both. Retrieving multiple data words when only one is needed wastes power, while performing multiple single-word reads for sequential data can also be inefficient. (’046 Patent, col. 2:1-15).
• The Patented Solution: The invention discloses a random access memory architecture capable of dynamically switching its read mode. It can retrieve a single data word in one clock cycle for random read requests to conserve power. Conversely, for burst read requests (where sequential data is needed), it can retrieve more than one data word in a single clock cycle, which is more power-efficient than executing multiple, separate read cycles. (’046 Patent, Abstract; col. 2:45-68). The overall memory architecture is depicted in Figure 1. (’046 Patent, Fig. 1).
• Technical Importance: This approach sought to provide greater power efficiency and performance flexibility in DRAMs, allowing the same memory chip to operate efficiently for both random access patterns (common in cache applications) and sequential access patterns (common in main memory operations). (’046 Patent, col. 2:18-28).

Key Claims at a Glance

• The complaint does not identify specific asserted claims for the ’046 Patent. It alleges infringement of "one or more claims" and incorporates by reference "Exemplary '046 Patent Claims" identified in an external chart (Exhibit 3) that was not provided with the filed complaint (Compl. ¶12).

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations," Issued June 6, 2006

The Invention Explained

• Problem Addressed: The patent addresses power consumption in DRAMs during standby or reduced power modes. In such modes, the current required to periodically refresh all memory cells can be a significant power drain, especially for battery-powered devices. This is inefficient if only a small portion of the memory contains data that needs to be retained. (’960 Patent, col. 1:29-56).
• The Patented Solution: The invention proposes a memory architecture divided into multiple sections (e.g., quadrants). It includes control circuitry that can selectively perform background refresh operations on one or more of these sections while leaving the periphery array circuits for other sections inactive. This allows the device to refresh only the necessary portions of the memory array, thereby reducing standby power consumption. (’960 Patent, Abstract; col. 2:37-41). The architecture enabling this selective control is illustrated in Figure 3, which shows separate refresh control signals (REF0-REF3) for each quadrant. (’960 Patent, Fig. 3).
• Technical Importance: This method provides a mechanism for partial array self-refresh, a critical feature for mobile and low-power applications where retaining essential data in a small portion of memory during sleep modes can significantly extend battery life. (’960 Patent, col. 1:40-56).

Key Claims at a Glance

• The complaint does not identify specific asserted claims for the ’960 Patent. It alleges infringement of "one or more claims" and incorporates by reference "Exemplary '960 Patent Claims" identified in an external chart (Exhibit 4) that was not provided with the filed complaint (Compl. ¶18).

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, models, or services (Compl. ¶¶12, 18). It refers generally to "Exemplary Defendant Products" that are purportedly identified in external exhibits not included with the complaint (Compl. ¶¶14, 20).

Functionality and Market Context

The complaint alleges infringement through Defendant's acts of "making, using, offering to sell, selling and/or importing" the unspecified products (Compl. ¶¶12, 18). Given that the Defendant is a bank, these allegations suggest the accused instrumentalities may be standard computer hardware, such as servers, workstations, or networking equipment, used in the course of its business operations. The complaint does not provide sufficient detail for analysis of the accused functionality. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not contain a narrative infringement theory or identify asserted claims in its body. Instead, it incorporates by reference claim charts from Exhibits 3 and 4, which were not provided with the complaint (Compl. ¶¶15, 21). As a result, a claim chart summary cannot be constructed, and no specific points of contention can be identified from the pleading.

V. Key Claim Terms for Construction

The complaint does not provide sufficient detail for analysis of key claim terms, as it fails to identify any specific claims of the patents-in-suit that are asserted against the Defendant.

VI. Other Allegations

The complaint contains counts only for direct infringement and does not include allegations to support claims of indirect or willful infringement (Compl. ¶¶11-22).

VII. Analyst’s Conclusion: Key Questions for the Case

The complaint’s sparse allegations raise threshold questions that will likely define the initial phase of this litigation.

• A primary issue will be one of pleading sufficiency: does the complaint’s failure to identify any specific accused products, asserted patent claims, or operative facts supporting infringement meet the plausibility standard required by federal pleading rules and any applicable local patent rules? The court may need to resolve whether these general allegations provide the Defendant with adequate notice of the infringement claims against it.
• A central question of liability will be how a financial institution's use of commercially available computing equipment could constitute direct infringement of patents directed to the internal architecture of semiconductor memory components. The case may turn on whether Plaintiff can establish that the mere "use" of end-products containing allegedly infringing memory chips satisfies the elements of the asserted claims.