DCT

1:24-cv-00254

Vervain LLC v. Kingston Technology Co Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:24-cv-00254, W.D. Tex., 05/10/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants have committed acts of infringement in the district and maintain a regular and established place of business, citing a physical office in Round Rock, TX, and the presence of an Austin-based employee.
  • Core Dispute: Plaintiff alleges that Defendant’s flash memory products, including solid-state drives (SSDs) and memory cards, infringe eight patents related to systems and methods for managing data in memory architectures that combine both multi-level cell (MLC) and single-level cell (SLC) non-volatile memory.
  • Technical Context: The technology addresses the trade-offs in flash memory design, where less-durable but high-capacity MLC memory is paired with more-durable but lower-capacity SLC memory to create storage devices that balance performance, longevity, and cost.
  • Key Procedural History: The asserted patents are part of a large, interrelated family originating from a 2011 provisional application, with several patents having issued in late 2023 and 2024, shortly before the complaint was filed. The complaint notes that in prior, unrelated litigation, Kingston declined to dispute that venue was proper in the Western District of Texas.

Case Timeline

Date Event
2011-07-19 Priority Date for all Asserted Patents
2014-11-18 U.S. Patent No. 8,891,298 Issues
2015-11-24 U.S. Patent No. 9,196,385 Issues
2018-06-12 U.S. Patent No. 9,997,240 Issues
2021-03-16 U.S. Patent No. 10,950,300 Issues
2023-11-28 U.S. Patent No. 11,830,546 Issues
2023-12-26 U.S. Patent No. 11,854,612 Issues
2024-04-23 U.S. Patent No. 11,967,369 Issues
2024-04-23 U.S. Patent No. 11,967,370 Issues
2024-05-10 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,891,298 - “Lifetime Mixed Level Non-Volatile Memory System”

The Invention Explained

  • Problem Addressed: The patent’s background section describes the trade-offs between different types of non-volatile memory. Multi-level cell (MLC) NAND flash offers high storage density at a low cost but suffers from limited endurance (i.e., a low number of write-erase cycles) and slower performance compared to single-level cell (SLC) NAND flash, which is faster and more durable but more expensive and less dense (’298 Patent, col. 3:36-52; Compl. ¶49).
  • The Patented Solution: The invention proposes a hybrid memory system managed by a controller that combines the benefits of both memory types. The controller uses the lower-cost MLC memory for general storage while strategically employing the high-endurance SLC memory for two primary purposes: 1) as a safe location to remap data from MLC blocks that are failing data integrity tests, and 2) as a designated area for blocks that are identified as receiving the most frequent writes, thereby extending the operational lifetime of the entire memory system (’298 Patent, Abstract; col. 4:1-9).
  • Technical Importance: This hybrid architecture allows for the creation of cost-effective, high-capacity solid-state storage that mitigates the inherent endurance limitations of MLC technology, a key factor in the widespread adoption of SSDs (Compl. ¶49).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶60).
  • Claim 1 recites a system comprising:
    • At least one MLC non-volatile memory module and at least one SLC non-volatile memory module.
    • A controller coupled to the modules that is adapted to:
      • Maintain an address map that maps logical addresses to physical addresses in either the MLC or SLC module.
      • Determine if a range of addresses in the MLC module fails a data integrity test and, upon failure, remap that entry to an available range in the SLC module.
      • Determine which blocks are accessed most frequently by maintaining a count.
      • Allocate blocks with the most frequent writes by transferring their contents to the SLC module.

U.S. Patent No. 9,196,385 - “Lifetime Mixed Level Non-Volatile Memory System”

The Invention Explained

  • Problem Addressed: As a continuation of the application leading to the ’298 Patent, this patent addresses the same technical challenge of managing a hybrid MLC/SLC memory system to optimize for cost, performance, and endurance (’385 Patent, col. 1:10-21).
  • The Patented Solution: The invention is embodied in a "flash translation layer" (FTL), which is described as the firmware or logic within a controller responsible for managing the memory. The FTL performs the core functions of the invention: it maintains the logical-to-physical address map, conducts data integrity tests on MLC blocks, remaps failed blocks to the SLC module, and uses access counts to identify and relocate frequently written blocks to the more durable SLC memory, thereby improving the system's overall lifespan (’385 Patent, col. 2:66-col. 3:12; Abstract).
  • Technical Importance: By defining these management functions within the FTL, the patent describes a common architectural component in modern SSDs responsible for making the complex behavior of flash memory transparent to the host computer system (Compl. ¶100).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶95).
  • Claim 1 recites a system comprising:
    • At least one MLC module and at least one SLC module.
    • A flash translation layer (FTL) adapted to perform functionally identical steps as the controller in claim 1 of the ’298 Patent: maintain an address map, test data integrity and remap failed MLC blocks to SLC, and count block accesses to move frequently written data to SLC.

U.S. Patent No. 9,997,240 - “Lifetime Mixed Level Non-Volatile Memory System”

  • Technology Synopsis: This patent continues the theme of the parent patents, describing a memory controller that manages a hybrid SLC/MLC system. The claims introduce the concepts of designating blocks as "hot blocks" (for frequent writes to SLC) and "cold blocks" (for infrequent writes to MLC) and periodically transferring the contents of frequently accessed blocks to the SLC module when a predetermined count value is reached.
  • Asserted Claims: At least claim 6 (Compl. ¶110).
  • Accused Features: The complaint alleges that the controllers in the Accused Products perform these functions through wear-leveling algorithms and SLC caching/copyback procedures (Compl. ¶¶115-117).

U.S. Patent No. 10,950,300 - “Lifetime Mixed Level Non-Volatile Memory System”

  • Technology Synopsis: This patent claims a system where a controller performs a data integrity test on data stored in an MLC element by comparing it to a copy of that data retained in a random access volatile memory (e.g., DRAM/SRAM). If the comparison fails, the system remaps the address space and transfers the data to achieve enhanced endurance.
  • Asserted Claims: At least claim 1 (Compl. ¶123).
  • Accused Features: The allegations target the use of DRAM or SRAM caches in the Accused Products, where data is temporarily held during a write operation and can be used to verify the data successfully written to the MLC flash memory (Compl. ¶¶131-132).

U.S. Patent No. 11,830,546 - “Lifetime Mixed Level Non-Volatile Memory System”

  • Technology Synopsis: This patent is similar to the ’300 Patent, claiming a system where the controller uses an associated "controller memory" to store received data. It performs a data integrity test by reading the data back from the MLC module to the controller memory and comparing it against a retained copy that was associated with the stored data during the write operation.
  • Asserted Claims: At least claim 1 (Compl. ¶140).
  • Accused Features: The accused functionality is the use of DRAM/SRAM caches within the controllers to temporarily store write data and perform read-after-write verification to ensure data integrity (Compl. ¶¶147-148).

U.S. Patent No. 11,854,612 - “Lifetime Mixed Level Non-Volatile Memory System”

  • Technology Synopsis: This patent claims a method for storing data that mirrors the system claims of related patents. The method includes maintaining an address table for a hybrid memory space, controlling write operations, storing received data in a controller memory, performing a data integrity test by reading data from the MLC memory and comparing it to data retained in volatile memory from the write operation, and remapping/transferring data upon test failure.
  • Asserted Claims: At least claim 1 (Compl. ¶156).
  • Accused Features: The accused activity is the operation of the Accused Products when used by Kingston or its customers, which allegedly performs the claimed method steps (Compl. ¶¶157-169).

U.S. Patent No. 11,967,369 - “Lifetime Mixed Level Non-Volatile Memory System”

  • Technology Synopsis: This patent claims a system with a more detailed memory architecture, specifying "logical and physical" volatile and nonvolatile memory spaces. The core inventive concept remains a data integrity test performed by the controller, which compares data written to a physical MLC element against a copy retained in random access volatile memory, with remapping of the logical address space upon failure.
  • Asserted Claims: At least claim 1 (Compl. ¶175).
  • Accused Features: The accused functionality involves the controllers' use of L2P tables to map logical to physical addresses and the use of RAM to cache data for write verification (Compl. ¶¶177-189).

U.S. Patent No. 11,967,370 - “Lifetime Mixed Level Non-Volatile Memory System”

  • Technology Synopsis: This patent claims a system where the controller performs a data integrity test based on "received data retained at the controller." Upon failure of the test, the controller remaps the logical entry to an available physical range in the SLC module and transfers the stored data from the failed MLC location to the new SLC location.
  • Asserted Claims: At least claim 1 (Compl. ¶198).
  • Accused Features: The allegations target the controllers' defect and error management technologies, which use data retained in controller memory (e.g., RAM) to perform integrity tests on data written to MLC flash and move data upon failure (Compl. ¶¶207-208).

III. The Accused Instrumentality

Product Identification

The complaint identifies a broad range of Kingston's flash memory products, including numerous models of SSDs (e.g., XS2000, DC1500M, NV2, FURY Renegade), USB flash drives, memory cards, and embedded flash products (collectively, the “Accused Products”) (Compl. ¶¶53-54).

Functionality and Market Context

The Accused Products are data storage devices that employ controller chips, primarily from Phison and Silicon Motion, to manage data on NAND flash memory (Compl. ¶¶9, 53). The complaint alleges these controllers implement a hybrid memory architecture that uses high-density MLC memory (such as TLC or QLC) for bulk storage and a smaller portion of high-endurance SLC memory, often operated as an "SLC buffer" or "SLC Caching" system, to improve performance and product lifespan (Compl. ¶¶12, 63). An image from a Phison blog post shows a diagram of this architecture, where write data from a host first enters an "SLC buffer" before being internally copied to a "TLC mode" area (Compl. ¶63; Ex. Z). These products are positioned as high-speed, reliable storage solutions for a variety of markets, from consumer PCs to enterprise servers (Compl. ¶9).

IV. Analysis of Infringement Allegations

8,891,298 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a) maintain an address map of at least one of the MLC and SLC non-volatile memory modules... The controllers in the Accused Products use a logical-to-physical (L2P) mapping table to track the relationship between logical blocks accessible by a host system and the physical addresses of the flash memory. ¶67 col. 4:1-9
b) determine if a range of addresses... within the at least one MLC non-volatile memory module, fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the next available... range... within the at least one SLC non-volatile memory module; The controllers' firmware (e.g., Phison's "SmartRefresh" or Silicon Motion's "IntelligentScan & DataRefresh") runs in the background to check for error bits in data blocks. Upon detecting a failure (e.g., error bits exceeding a threshold), the firmware remaps the degraded data to a new location, which the complaint alleges is in the SLC module. ¶73 col. 6:1-11
c) determine which of the blocks... are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed; The controllers employ wear-leveling algorithms that use count data, such as program/erase (P/E) counts, to monitor the usage of each block. ¶81 col. 6:29-32
d) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory module. The controllers' SLC caching technology and "count balance scheme" are used to move frequently accessed or written data to the SLC NAND area. ¶¶84-85 col. 6:32-35

9,196,385 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a flash translation layer (FTL); wherein the FTL is adapted to: The controllers in the Accused Products, such as those from Phison, include a proprietary Flash Translation Layer (FTL) that manages the underlying memory operations. An image from Phison's website explicitly labels this technology "FLASH TRANSLATION LAYER" (Compl. ¶100; Ex. II). ¶100 col. 2:51-53
a) maintain an address map... The FTL provides mapping between logical and physical addresses using a data structure such as an L2P table. ¶101 col. 4:18-28
b) determine if a range of addresses... within the at least one MLC non-volatile memory module, fails a data integrity test, and... remaps the entry to... the at least one SLC non-volatile memory module; The controllers, via the FTL, perform data integrity functions and remap data to SLC memory upon the failure of a data integrity test. ¶102 col. 4:29-37
c) determine which of the blocks... are accessed most frequently by maintaining a count... The FTL utilizes various block counting mechanisms as part of its wear-leveling and data management functions. ¶103 col. 4:38-41
d) allocate those blocks that receive the most frequent writes by transferring the respective contents... to the at least one SLC non-volatile memory module. The FTL allocates frequently written blocks to be transferred to the SLC memory area. ¶104 col. 4:42-45

Identified Points of Contention

  • Scope Questions: A central question may be whether the accused SLC caching functionality, which often serves as a high-speed buffer for all incoming write data, meets the specific claim limitation of "allocat[ing] those blocks that receive the most frequent writes" by transferring them. A defendant could argue that a universal write buffer operates differently than a targeted relocation mechanism for pre-identified "hot" blocks.
  • Technical Questions: The infringement theory for the "data integrity test" limitation relies on the controllers' general error detection and data refresh features (e.g., checking ECC bits). A key technical question will be whether a "failure" of such a test, as implemented in the accused devices, necessarily and directly results in remapping the data to the SLC module, as required by the claims, or whether data is more commonly remapped to another available MLC block as part of standard garbage collection and wear-leveling.

V. Key Claim Terms for Construction

  • The Term: "fails a data integrity test" (from ’298 Patent, Claim 1)

  • Context and Importance: This term is critical because it defines the trigger for the claimed remapping from MLC to SLC. The complaint construes this broadly to include standard error-bit monitoring performed by the controller's firmware (Compl. ¶74). Practitioners may focus on this term to dispute whether exceeding a correctable error bit threshold constitutes a "failure" in the claimed sense, or if a more catastrophic, uncorrectable error is required.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification does not limit the test to a specific kind, stating generally that the controller "conducts a data integrity check to ensure that the data was written correctly" (’298 Patent, col. 4:15-17). This could support an interpretation that includes any form of error checking.
    • Evidence for a Narrower Interpretation: The flowchart in Figure 3B depicts the test as a direct "Compare Data Written... to Data Read" step (element 114), which results in a binary "Match?" decision (element 116). A defendant may argue this implies a specific read-after-write comparison, not just a passive check of ECC bits that might be corrected on-the-fly.

  • The Term: "allocate those blocks that receive the most frequent writes by transferring the respective contents... to the at least one SLC non-volatile memory module" (from ’298 Patent, Claim 1)

  • Context and Importance: This term links the "counting" function to the specific action of moving frequently written blocks to the SLC area. The complaint equates this with the operation of an SLC cache (Compl. ¶¶84-85). Practitioners may focus on whether an SLC cache, which often acts as a temporary buffer for all incoming writes to improve burst speed, is structurally and functionally the same as a system that first identifies a block as "frequently written" over time and then transfers its existing contents to a designated long-term SLC area.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes a general goal of segregating blocks, stating the controller "segregates those blocks that receive frequent writes into the at least one SLC non-volatile memory module and those blocks that receive infrequent writes into the at least one MLC nonvolatile module" (’298 Patent, col. 4:48-53). This supports a policy-based interpretation that could cover various implementation methods.
    • Evidence for a Narrower Interpretation: The claim language requires "transferring the respective contents" of blocks that "receive the most frequent writes." This could be interpreted to mean moving an existing block from MLC to SLC after it has been identified as "hot" through counting. An architecture where all new data is simply directed to an SLC write buffer first might not meet this specific "transferring" limitation.

VI. Other Allegations

  • Indirect Infringement: While the complaint's formal counts are for direct infringement under 35 U.S.C. § 271(a), the allegations for the asserted method claims (e.g., for the ’612 Patent) are based on the actions of the Accused Products "when used by Kingston or its customers" (Compl. ¶¶157-169). This suggests a potential future argument for induced infringement.
  • Willful Infringement: The complaint does not use the term "willful." However, for each asserted patent, it alleges that the case is "exceptional" and requests attorneys' fees under 35 U.S.C. § 285 (e.g., Compl. ¶93, 107, 120). Such a request is often predicated on allegations of willful or egregious conduct that may be developed during discovery.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of functional equivalence: Do the accused controllers' SLC caching mechanisms, which are often designed to accelerate burst write performance for all incoming data, perform the specific claimed function of identifying blocks with the "most frequent writes" over time and then "transferring" their contents to the SLC module for long-term endurance benefits?
  • A key evidentiary question will be one of operational reality: When the accused products' error management systems detect that a data block in MLC memory has exceeded an error bit threshold (i.e., "fails a data integrity test"), what is the actual, programmed response? Is the data automatically remapped to the SLC module as the claims require, or is it typically relocated to a different, healthy MLC block as part of routine garbage collection, with relocation to the SLC module being a more rare or non-existent event?