DCT

1:24-cv-00259

Vervain LLC v. Phison Electronics Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:24-cv-00259, W.D. Tex., 05/13/2024
  • Venue Allegations: Plaintiff asserts venue is proper because Defendant is not a resident of the United States and may be sued in any judicial district. Alternatively, Plaintiff alleges venue is proper based on Defendant’s commission of infringing acts and maintenance of a regular and established place of business in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s flash memory controllers, solid-state drives (SSDs), and other non-volatile memory products infringe eight U.S. patents related to managing hybrid memory systems that combine multi-level cell (MLC) and single-level cell (SLC) flash memory to enhance device lifetime and reliability.
  • Technical Context: The technology addresses the challenge of balancing cost, storage density, and endurance in flash memory devices by using a small amount of high-endurance SLC memory to augment a larger, more cost-effective but less durable bank of MLC memory.
  • Key Procedural History: The complaint alleges that Defendant gained knowledge of the asserted patent portfolio on or before July 18, 2022, through subpoenas served in related litigation involving the same patent family (Vervain, LLC v. Micron Tech., Inc. and Vervain, LLC v. Western Digital Corp.), a fact which may be material to claims of willful infringement.

Case Timeline

Date Event
2000-11-01 Phison Electronics Corporation established
2010-11-01 Phison and Kingston form joint venture
2011-07-19 Earliest Priority Date for all Asserted Patents
2014-11-18 U.S. Patent No. 8,891,298 Issues
2015-11-24 U.S. Patent No. 9,196,385 Issues
2018-06-12 U.S. Patent No. 9,997,240 Issues
2021-03-16 U.S. Patent No. 10,950,300 Issues
2022-07-18 Subpoenas served on Phison in related litigation
2023-11-28 U.S. Patent No. 11,830,546 Issues
2023-12-26 U.S. Patent No. 11,854,612 Issues
2024-04-23 U.S. Patent No. 11,967,369 Issues
2024-04-23 U.S. Patent No. 11,967,370 Issues
2024-05-13 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,891,298 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: November 18, 2014.

The Invention Explained

  • Problem Addressed: The patent addresses the inherent trade-offs in NAND flash memory technology. Multi-level cell (MLC) flash offers high storage density at a low cost but suffers from low endurance (a limited number of write cycles). Conversely, single-level cell (SLC) flash has much higher endurance and faster access speeds but is significantly more expensive and less dense (’298 Patent, col. 2:38-54). The technical problem is how to create a storage system that achieves a long operational lifetime without incurring the high cost of an all-SLC design.
  • The Patented Solution: The invention proposes a hybrid memory system managed by a controller that dynamically allocates data between MLC and SLC modules to extend the overall life of the device. The controller performs two key functions: (1) if a write to a block in the MLC module fails a data integrity test, the controller remaps that data to an available block in the high-endurance SLC module; and (2) the controller monitors data access patterns, identifies "hot" blocks that are written to frequently, and proactively moves their contents to the SLC module to prevent premature wear on the MLC memory (’298 Patent, col. 6:14-35, col. 6:53-65).
  • Technical Importance: This memory management strategy was a key enabling technology for making SSDs commercially viable for consumer and enterprise applications by improving reliability and endurance while controlling costs (Compl. ¶44).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶61).
  • The essential elements of Claim 1 are:
    • A system with at least one MLC module and at least one SLC module.
    • A controller that maintains an address map for both modules.
    • The controller is adapted to determine if a write to the MLC module fails a data integrity test.
    • Upon such a failure, the controller remaps the corresponding address entry to an available range in the SLC module.
    • The controller is also adapted to determine which blocks are most frequently accessed by maintaining an access count.
    • The controller allocates these frequently written blocks by transferring their contents to the SLC module.
  • The complaint reserves the right to identify additional infringing products and activities during discovery (Compl. ¶61).

U.S. Patent No. 9,196,385 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: November 24, 2015.

The Invention Explained

  • Problem Addressed: As a continuation of the application leading to the ’298 Patent, this patent addresses the same technical problem of balancing cost, performance, and endurance in a non-volatile memory system by combining MLC and SLC flash technologies (’385 Patent, col. 2:38-54).
  • The Patented Solution: The solution is functionally identical to that of the ’298 Patent but is claimed from the perspective of a specific architectural component: the "flash translation layer" (FTL). The FTL is described as the firmware or logic responsible for managing the address map, remapping data from MLC to SLC upon a data integrity failure, and allocating frequently written data to the SLC module to prolong device life (’385 Patent, col. 4:3-11).
  • Technical Importance: Framing the invention in terms of an FTL aligns the claims with the standard industry architecture for flash memory controllers, where the FTL is the component that handles logical-to-physical address mapping and wear-leveling functions (Compl. ¶99).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶91).
  • The essential elements of Claim 1 are:
    • A system with at least one MLC module and at least one SLC module.
    • A flash translation layer (FTL).
    • The FTL is adapted to maintain an address map for both modules.
    • The FTL determines if a write to the MLC module fails a data integrity test and, upon failure, remaps the address to the SLC module.
    • The FTL determines frequently accessed blocks by maintaining a count.
    • The FTL allocates these frequently written blocks by transferring their contents to the SLC module.
  • The complaint reserves the right to assert infringement by additional products or services identified in discovery (Compl. ¶91).

U.S. Patent No. 9,997,240 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: June 12, 2018.
  • Technology Synopsis: This patent continues the same technological theme, claiming a system that manages MLC and SLC memory. Its claims add specificity by introducing the concepts of designating frequently written blocks as "hot blocks" for the SLC module and infrequently written blocks as "cold blocks" for the MLC module, and transferring data between them based on a "predetermined count value" being reached (’240 Patent, Abstract).
  • Asserted Claims: At least independent claim 6 (Compl. ¶112).
  • Accused Features: The complaint alleges that Phison's controllers, which use block counting and transfer frequently written blocks to SLC memory based on count values, infringe this patent (Compl. ¶117, ¶119).

U.S. Patent No. 10,950,300 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: March 16, 2021.
  • Technology Synopsis: This patent claims a system architecture that explicitly includes MLC and SLC nonvolatile memory elements, a controller, and "at least one random access volatile memory" (e.g., DRAM). The claimed data integrity test involves comparing data stored in the MLC element with data retained in the volatile RAM after a write operation, and remapping upon failure (’300 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶124).
  • Accused Features: The accused features include Phison controllers that use DRAM or SRAM for caching and to store logical-to-physical mapping tables, and which perform data integrity checks using this volatile memory (Compl. ¶134, ¶137).

U.S. Patent No. 11,830,546 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: November 28, 2023.
  • Technology Synopsis: This patent is directed to a similar system including MLC/SLC nonvolatile memory and random access volatile memory. The claims specify that the controller has an associated "controller memory" (e.g., a buffer or cache) and performs a data integrity test by reading stored data from an MLC module back to this controller memory and comparing it against data retained in the volatile memory from the write operation (’546 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶144).
  • Accused Features: The complaint accuses Phison products that cache written data in RAM and perform data integrity tests by comparing data stored in flash with the data retained in the controller's cache (Compl. ¶155-156).

U.S. Patent No. 11,854,612 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: December 26, 2023.
  • Technology Synopsis: This patent claims a method for storing data, rather than a system. The recited steps mirror the functions of the systems in the parent patents, including maintaining an address table, mapping addresses, controlling access to MLC/SLC modules, storing data in a controller memory, performing a data integrity test by comparing stored and retained data, and remapping upon failure (’612 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶163).
  • Accused Features: The accused functionality is the operation of Phison’s controllers and flash memory products, which allegedly perform the claimed method steps (Compl. ¶168).

U.S. Patent No. 11,967,369 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: April 23, 2024.
  • Technology Synopsis: This patent claims a memory system with specific recitations of "logical and physical" memory spaces for both volatile and nonvolatile memory. The core invention remains the management of a hybrid MLC/SLC system, including data integrity checks and remapping upon failure, but with claim language that more explicitly defines the memory address architecture (’369 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶185).
  • Accused Features: The complaint accuses Phison products that use logical block numbers and physical memory mappings, including host memory buffers that address volatile memory, of infringing (Compl. ¶191-192).

U.S. Patent No. 11,967,370 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Issued: April 23, 2024.
  • Technology Synopsis: This patent claims a system where the data integrity test is specified as being "performed at the controller based upon received data retained at the controller." This language emphasizes that the reference data for the integrity check is held within the controller itself (e.g., in a cache or buffer) during the verification process (’370 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶211).
  • Accused Features: The complaint accuses Phison controllers that incorporate defect and error management technology using data retained at the controller to perform integrity tests on data stored in MLC flash memory (Compl. ¶224).

III. The Accused Instrumentality

Product Identification

  • The complaint broadly defines the "Accused Products" to include Phison’s flash memory controllers (e.g., PS5026-E26, SA50), finished SSDs, USB memory cards, and embedded flash products. The allegations also extend to third-party products that incorporate these Phison controllers, from brands including Kingston, ADATA, Corsair, Seagate, and others (Compl. ¶52, ¶53).

Functionality and Market Context

  • The accused products are alleged to be high-capacity, high-speed storage devices that employ a hybrid memory architecture (Compl. ¶9). A core accused feature is the use of an "SLC cache" or "SLC buffering system," where incoming data is first written to a fast, high-endurance SLC portion of memory before being moved to a denser, lower-endurance MLC, TLC, or QLC portion (Compl. ¶9, ¶67).
  • The complaint alleges Phison’s controllers use a logical-to-physical (L2P) mapping table to manage the physical location of data on the flash memory array (Compl. ¶71-72). An accompanying diagram shows the controller referencing this L2P table, which is stored in both NAND flash and DRAM (Compl. Ex. Z, p. 21).
  • The products are alleged to include firmware for error management and endurance enhancement, such as "SmartRefresh" technology, which checks for data errors, and "Adaptive Wear Leveling," which moves data to prolong the life of the NAND cells (Compl. ¶75, ¶76). The complaint alleges that upon detecting a data integrity failure, the controllers remap data to a new location, including from MLC to SLC blocks (Compl. ¶76-77).

IV. Analysis of Infringement Allegations

8,891,298 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
...at least one MLC non-volatile memory module... Accused Products use MLC, TLC, or QLC memory, which function as multi-level cell memory. ¶67 col. 2:38-42
...at least one SLC non-volatile memory module... Accused Products utilize SLC caching systems and SLC buffers. ¶69 col. 2:38-42
...a controller coupled to the at least one MLC... and the at least one SLC... module Phison's SSDs include Phison controllers, and its controller products are themselves controllers coupled to memory modules. ¶70 col. 5:21-27
a) maintain an address map... wherein each entry... maps to a similar range of physical addresses within either the... SLC... or... MLC... module Phison controllers use a logical-to-physical (L2P) mapping table to track the relationship between logical blocks and physical addresses in flash memory. ¶71-72 col. 5:42-50
b) determine if a range of addresses... within the... MLC... module, fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the next available equivalent range of physical addresses within the... SLC... module Phison controllers incorporate defect and error management technology (e.g., "SmartRefresh") that performs data integrity tests and remaps degraded data to a new location, including moving data from MLC to SLC. ¶74-77 col. 6:24-35
c) determine which of the blocks... are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed Phison controllers use block counting mechanisms, such as program/erase counts, as part of their wear-leveling schemes to determine block access frequency. ¶79-80 col. 6:36-41
d) allocate those blocks that receive the most frequent writes by transferring the respective contents... to the at least one SLC non-volatile memory module Phison controllers use a "count balance scheme" to transfer frequently written blocks to SLC memory and employ garbage collection that can relocate frequently accessed data. ¶81-83 col. 6:42-46

9,196,385 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
...at least one MLC non-volatile memory module... Accused Products store data in MLC, TLC, or QLC memory. ¶97 col. 2:38-42
...at least one SLC non-volatile memory module... Accused Products store data in SLC memory as part of an SLC caching system. ¶98 col. 2:38-42
...a flash translation layer (FTL)... Accused Products include an FTL that uses an L2P table to map between logical and physical addresses. ¶99 col. 3:3-11
a) maintain an address map... The FTL in the Accused Products uses an L2P table for mapping, with a minimum quanta such as a page. ¶100 col. 4:3-11
b) determine if a range of addresses... within the... MLC... module, fails a data integrity test, and... remaps the entry to the... SLC... module Controllers in the Accused Products perform data integrity functions and remap data to SLC memory upon test failure. ¶101 col. 4:12-21
c) determine which of the blocks... are accessed most frequently by maintaining a count... A variety of block counting mechanisms are present in the Accused Products to track access frequency. ¶102 col. 4:22-26
d) allocate those blocks that receive the most frequent writes by transferring the respective contents... to the... SLC... module Frequently written blocks are allocated and their contents are transferred to SLC memory. ¶103 col. 4:27-31

Identified Points of Contention

  • Scope Questions: A primary question may be whether the term "MLC non-volatile memory module" from the 2011-priority patents can be construed to read on the modern TLC (Triple-Level Cell) and QLC (Quad-Level Cell) flash technologies used in the Accused Products (Compl. ¶9, ¶67). While TLC and QLC are technically types of multi-level cells, the defense may argue that the term, in the context of the patent, was understood by a person of ordinary skill in the art at the time to refer to technology storing only two bits per cell.
  • Technical Questions: The complaint alleges that upon a data integrity failure, the controller remaps the entry to the SLC module (Compl. ¶74, ¶76). A key technical question will be what evidence demonstrates this specific causal link. The defense may contend that while the accused products perform both error correction and data relocation (including to SLC cache), the trigger for remapping to SLC is based on wear-leveling or caching algorithms, not necessarily the failure of a specific "data integrity test" as required by the claim language.
  • Scope Questions: Another question may arise regarding the functional elements of counting accesses (claim 1c) and allocating frequent writes to SLC (claim 1d). The defense could argue that these are not two distinct, inventive steps but are integrated aspects of a single, conventional wear-leveling algorithm, and that the claims improperly attempt to monopolize this well-known technique through functional claiming.

V. Key Claim Terms for Construction

  • The Term: "fails a data integrity test"

    • Context and Importance: This phrase is the direct trigger for the claimed remapping from an MLC module to an SLC module, a core feature of the invention. The definition of what constitutes such a "test" and "failure" is central to the infringement analysis, as it distinguishes the claimed invention from routine data management. Practitioners may focus on whether this requires a specific post-write verification process or if it can encompass any form of error detection, such as standard Error Correction Code (ECC) checks.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The term itself is not explicitly defined in the claims, which may support an argument for its plain and ordinary meaning, covering any test that verifies the correctness of data, including the ECC-based "SmartRefresh" technology alleged to be in the accused products (Compl. ¶75).
      • Evidence for a Narrower Interpretation: The detailed description suggests a specific implementation: "After each write... the device controller 14 will as time permits perform a read on the address range to ensure the integrity of the written data" (’298 Patent, col. 6:24-28). The patent's flowchart also depicts a step of comparing "Data Written" to "Data Read" from the same physical address range (’298 Patent, Fig. 3B, step 114). This may support a narrower construction limited to a read-after-write verification, as opposed to more general background error monitoring.

  • The Term: "allocate those blocks that receive the most frequent writes by transferring the respective contents"

    • Context and Importance: This limitation describes the proactive, wear-leveling aspect of the invention. Its construction will determine whether the accused SLC caching mechanisms, which temporarily store new writes before moving them to MLC memory (Compl. ¶9), perform the claimed function. The dispute may center on whether "transferring the respective contents" of an existing, frequently-written block is the same as caching new writes destined for a logical address that happens to be "hot."
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent's background discusses the general problem of "hot" blocks wearing out, and the summary describes segregating blocks with frequent writes into the SLC module (’298 Patent, col. 4:49-54). This could support a reading where any mechanism that results in frequently-written data residing in SLC memory meets the limitation.
      • Evidence for a Narrower Interpretation: The claim language recites "transferring the respective contents of those blocks," which suggests moving existing data from one location (MLC) to another (SLC). The complaint alleges Phison's SLC cache writes data "to the SLC cache first, and then data is moved to QLC" (Compl. ¶9). This describes a write-caching flow, which may be technically distinct from identifying an existing hot block in MLC and migrating its contents to SLC, as a defendant might argue the claim requires.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement on the basis that Phison provides user manuals and technical documentation that instruct customers and end-users to combine its controllers with memory components and operate them in ways that practice the claimed inventions (Compl. ¶62, ¶92). Contributory infringement is alleged on the grounds that Phison's products are a material part of the patented inventions, are not staple articles of commerce, and are especially made or adapted for use in an infringing manner (Compl. ¶63, ¶93).
  • Willful Infringement: Willfulness allegations are based on Phison's alleged knowledge of the asserted patent portfolio stemming from subpoenas it received on July 18, 2022, in two other patent infringement cases brought by Vervain against different defendants. The complaint alleges that Phison continued its infringing conduct despite this pre-suit knowledge of the patents (Compl. ¶48, ¶64).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can claim terms rooted in the 2011 priority date, such as "MLC non-volatile memory module" and "data integrity test," be construed to encompass modern technologies like QLC flash and the sophisticated, multi-faceted error management and caching algorithms (e.g., "SmartRefresh," "SLC Buffering") found in the accused products?
  • A key evidentiary question will be one of functional causality: does the evidence show that the accused products perform the specific sequence required by the claims—namely, that a "data integrity test" failure on an MLC block directly causes that block's logical address to be remapped to the SLC module—or are data remapping decisions driven primarily by independent wear-leveling and performance-caching logic?
  • The case will also turn on a question of technical distinction: do the accused products perform the separate claimed functions of (1) reactively remapping failed writes to SLC and (2) proactively moving frequently-written blocks to SLC, or are these claimed functions merely different descriptions of a single, integrated, and potentially conventional caching and wear-leveling architecture?