DCT

1:24-cv-00335

Concurrent Ventures LLC v. Advanced Micro Devices Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:24-cv-00335, W.D. Tex., 03/29/2024
  • Venue Allegations: Venue is alleged to be proper in the Western District of Texas because Defendants maintain a regular and established place of business in Austin, Texas, and have allegedly committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Data Processing Unit (DPU) products and related technology, acquired through its 2022 purchase of Pensando Systems, infringe five patents related to high-efficiency data processing, modular hardware platforms, and network optimization.
  • Technical Context: The technology concerns specialized processors designed to offload networking, storage, and security workloads from a data center's main CPUs, a critical strategy for improving performance and efficiency in modern cloud computing and enterprise infrastructure.
  • Key Procedural History: The complaint alleges that Defendant AMD was made aware of the asserted technology during detailed technical discussions under a Mutual Nondisclosure Agreement in June 2014, years before its acquisition of Pensando. This allegation forms the primary basis for the claim of willful infringement.

Case Timeline

Date Event
2013-12-06 Earliest Priority Date for ’596 and ’767 Patents
2014-06-01 Plaintiff's agent and AMD allegedly hold technical discussions under NDA
2014-12-30 U.S. Patent No. 8,924,596 Issues
2016-12-27 U.S. Patent No. 9,529,767 Issues
2018-07-15 Earliest Priority Date for ’753, ’943, and ’634 Patents
2020-12-22 U.S. Patent No. 10,873,753 Issues
2021-03-09 U.S. Patent No. 10,944,634 Issues
2021-04-20 U.S. Patent No. 10,985,943 Issues
2022-01-01 AMD acquires Pensando Systems (approximate date)
2024-03-29 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,924,596 - System and Method for Dividing and Synchronizing a Processing Task Across Multiple Processing Elements/Processors in Hardware

  • Issued: December 30, 2014
  • The Invention Explained:
    • Problem Addressed: When processing tasks are distributed across multiple processors that all need to issue commands to a shared hardware queue, there is a risk of overfilling the queue. Traditional software-based synchronization methods, such as semaphores, are too slow and create performance bottlenecks. (’596 Patent, col. 1:15-34).
    • The Patented Solution: The patent describes a hardware-based synchronization system. A central "reservation register" stores a value indicating the amount of available space in a command queue. When a processor needs to issue a command, it reads this register. The hardware automatically decrements the stored value upon being read, effectively "reserving" a slot, and returns the pre-decrement value to the processor. This allows multiple processors to coordinate access to the queue at hardware speed without software overhead. (’596 Patent, Abstract; col. 4:14-30).
    • Technical Importance: This hardware-managed approach to queue synchronization provides a low-latency method for coordinating tasks among multiple processing elements, which is critical for high-performance data processing offload engines.
  • Key Claims at a Glance:
    • The complaint asserts independent claim 1. (Compl. ¶34).
    • Essential elements of claim 1 include:
      • A system with an input queue and an output queue implemented in hardware.
      • A first processing element and at least one second processing element.
      • A hardware "reservation register" storing a value indicating available space in the input queue, accessible by both processing elements.
      • Computer storage with instructions for the second processing element to:
        • access the reservation register and read the stored value;
        • determine from the read value if space is available;
        • notify the first processing element to issue a command.
      • The first processing element then issues the command to the input queue and receives a response from the output queue.
    • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 10,873,753 - Hardware Defined Anything In A Platform With Swappable Pods, Message Interface, Sandboxes And Memory Superposition

  • Issued: December 22, 2020
  • The Invention Explained:
    • Problem Addressed: Dedicated hardware systems are fast but inflexible, making it expensive and time-consuming to adapt to new data processing applications or standards. Software-based systems are flexible but slower. (’753 Patent, col. 1:8-23).
    • The Patented Solution: The patent proposes a modular and reconfigurable computing platform built around "swappable pods or cards" within one or more chassis. These modules communicate over a standardized "Module Message Interface (MMI) network." The pods can contain a mix of hardware and software modules, including user-definable circuits (e.g., on an FPGA), allowing the system's architecture to be reconfigured to suit specific data flow tasks. Communication is managed via packets with a specific header structure for addressing modules. (’753 Patent, Abstract; col. 3:4-9).
    • Technical Importance: This architecture aims to combine the performance of dedicated hardware with the flexibility of software, enabling the creation of powerful and adaptable data processing systems.
  • Key Claims at a Glance:
    • The complaint asserts independent claim 1. (Compl. ¶49).
    • Essential elements of claim 1 include:
      • A platform with one or more "swappable pods or cards" in a chassis, coupled through a messaging interface network.
      • Each pod/card has hardware or software modules, with at least one having a portion for user-definable modules.
      • The pods/cards are user-configurable to implement data flow processing architectures.
      • A network supporting messaging-based communication using packets with a header containing a chassis identifier, a board identifier, a module identifier, an instance identifier, and a type identifier, allowing each module to be addressed.
    • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 10,985,943 - Hardware Defined Anything In A Platform With Swappable Pods, Message Interface, Sandboxes And Memory Superposition

  • Issued: April 20, 2021
  • Technology Synopsis: This patent, related to the ’753 Patent, focuses on the architecture within a programmable device. It describes a programmable logic device (PLD) partitioned into a first region containing a hardware-based router and a second region containing one or more "sandboxes" with user-definable circuits. A secure, lockable bridge controls access between the two regions, enabling a protected environment for user-customized hardware functions. (’943 Patent, Abstract; col. 5:19-39).
  • Asserted Claims: Independent claim 1. (Compl. ¶62).
  • Accused Features: The complaint alleges that the AMD DPU is a programmable device where the "packet buffer traffic manager" acts as the first region's router and the P4 programmable pipelines and ARM CPU cores constitute the second region's "sandboxes." (Compl. ¶¶65-67). A diagram in the complaint explicitly labels these regions on a block diagram of the accused "Capri" chip. (Compl. p. 27).

U.S. Patent No. 10,944,634 - Optimization for Network Connections

  • Issued: March 9, 2021
  • Technology Synopsis: The technology addresses the slow start-up time of network connections (e.g., TCP/IP), which must gradually ramp up to determine available bandwidth. The patented solution uses a "tuner server" that collects and stores performance parameters from past connections. When a new connection is initiated, the tuner server determines if it matches a past connection's geographical area and, if so, provides an optimized initial transmission bandwidth, bypassing the slow ramp-up period. (’634 Patent, Abstract; col. 2:32-50).
  • Asserted Claims: Independent claim 8. (Compl. ¶75).
  • Accused Features: The complaint alleges that the AMD Pensando SmartSwitch and DPUs function as the claimed system. They allegedly collect network telemetry (parameter values) at a "first endpoint," and a DPU running a "flow-based engine" acts as the "tuner server" to determine bandwidth for new connections based on a "flow state table" of past connections. (Compl. ¶¶77-79).

U.S. Patent No. 9,529,767 - System And Method For Abstracting SATA And/Or SAS Storage Media Devices Via A Full Duplex Queued Command Interface...

  • Issued: December 27, 2016
  • Technology Synopsis: The patent describes a system to simplify host interaction with different storage protocols (SATA and SAS). It introduces an "abstraction protocol" that provides a unified, high-performance, full-duplex command interface. A "master controller" communicates with the host using this abstraction, while one or more "edge controllers" located near the storage devices translate the abstract commands into the native SATA or SAS protocols. (’767 Patent, Abstract; col. 4:1-12).
  • Asserted Claims: Independent claim 1. (Compl. ¶87).
  • Accused Features: The complaint alleges that AMD's DPU-enabled systems create the claimed network. The DPU itself is alleged to serve as a "master controller," communicating with a host, while other DPUs can act as "edge controllers." The P4 programmable language is alleged to implement the "abstraction protocol" for software-defined storage, including NVMe virtualization. (Compl. ¶¶89, 91-92).

III. The Accused Instrumentality

Product Identification

  • The accused products are AMD's DPU technology and DPU-enabled systems, including AMD Pensando Data Processing Units (e.g., Giglio, Elba, Capri), the AMD Pensando Distributed Services Card (DSC), SmartNICs, SmartSwitches, and the associated Software-In-Silicon Development Kit (“SSDK”). (Compl. ¶29).

Functionality and Market Context

  • The accused products are specialized hardware accelerators designed to be installed in data center servers and network switches. (Compl. ¶36). Their primary function is to "offload infrastructure services from the computing CPU," such as networking, security (e.g., firewalls), and storage tasks, thereby freeing up the main CPU for application processing. (Compl. ¶36). The complaint alleges these products use a programmable P4 data pipeline and ARM cores, allowing for user-configurable data processing. (Compl. ¶¶51, 52). A complaint exhibit shows the architecture of the accused "Elba" DPU, highlighting its Network-on-Chip (NOC), P4 processing blocks, and ARM CPU cores. (Compl. p. 15).

IV. Analysis of Infringement Allegations

’596 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an input queue implemented in hardware; an output queue implemented in hardware The Accused Products include numerous hardware queues, such as P4 RxDMA (input) and P4 TxDMA (output) queues. ¶37 col. 4:51-53
a first processing element having access to said input queue and said output queue A host system CPU or Virtual Machines running on the system containing the DPU have access to the DPU's queues for scheduling operations. ¶38 col. 4:54-56
at least one second processing element in communication with said first processing element A second processing element within the DPU (e.g., ARM cores) is connected to the first processing element (host CPU) via internal interconnects and a PCIe interface. ¶39 col. 4:57-59
a reservation register implemented in hardware storing a value indicative of available space in said input queue... The Accused Products use a "doorbell" mechanism for the hardware queues, which allegedly initiates a scheduler to manage queue space and allows objects to be added. ¶40 col. 4:60-65
computer storage storing instructions, which when executed by said at least one second processing element: accesses said reservation register and reads said stored value; determines when said read value indicates available space...notifies said first processing element... The DPU's scheduler accesses the reservation register (doorbell) to read the stored value, determines available space, and notifies the first processing element (host) to issue a command. ¶41 col. 4:66-7:5
wherein said first processing element...issues said command to said input queue, and receives a response...from said output queue. The first processing element (host), once notified, issues a command via the host interface to the input queue and receives a response from the output queue. ¶42 col. 5:1-7

Identified Points of Contention:

  • Scope Questions: The complaint alleges a "doorbell" mechanism meets the "reservation register" limitation. (Compl. ¶40). A point of contention may arise over whether a "doorbell," which is often a write-based signaling mechanism to notify hardware of new work, functions in the same way as the claimed "reservation register," which the claim specifies is read to determine available space and thereby reserve a slot.
  • Technical Questions: What evidence does the complaint provide that the DPU's scheduler, when interacting with the "doorbell," performs the specific sequence of reading a value, determining space, and then notifying a separate processing element, as required by the claim?

’753 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
one or more swappable pods or cards in one or more chassis, coupled through a messaging interface network The AMD Pensando DSC is a swappable PCIe card that can be installed in a server chassis and supports the P4 programming language for messaging. ¶51, ¶52 col. 13:20-24
each of the one or more swappable pods or cards having one or more hardware modules or one or more software modules The Pensando DSC contains hardware modules (e.g., P4 pipelines) and software modules (e.g., programs running on ARM cores). ¶52 col. 13:25-27
one or more of the plurality of swappable pods or cards having a portion for user-definable hardware modules or user-definable software modules The Pensando DSC is user-definable via P4 for hardware modules and via programming of its ARM cores for software modules. ¶52 col. 13:28-31
the plurality of swappable pods or cards being user-configurable to implement data flow processing architectures The Accused Products, such as the SmartSwitch, are designed to be user-configurable to implement different data flow architectures. ¶53 col. 13:32-34
a network coupled to the one or more swappable pods or cards and supporting messaging-based communication using packets each having a header with a chassis identifier, a board identifier, a module identifier, an instance identifier, and a type identifier... The Pensando DPUs are programmable using P4, which allows for customization of how network devices process packets and their headers. ¶55 col. 13:35-44

Identified Points of Contention:

  • Scope Questions: The patent figures depict a proprietary system of "pods" in a custom chassis. (’753 Patent, Fig. 1A). A dispute may arise over whether an industry-standard PCIe card, like the accused Pensando DSC, falls within the scope of the term "swappable pods or cards" as used in the patent. The complaint provides an image of the accused DSC, a half-height, half-length PCIe card. (Compl. p. 20).
  • Technical Questions: The complaint alleges that the P4-programmable nature of the DPUs allows for custom packet processing. (Compl. ¶55). A key evidentiary question will be whether the accused products, as sold and used, actually implement a packet header that includes all five specific identifiers recited in the claim: chassis, board, module, instance, and type.

V. Key Claim Terms for Construction

For the ’596 Patent:

  • The Term: "reservation register"
  • Context and Importance: This term is the central innovation claimed for hardware-based synchronization. The plaintiff's infringement theory equates this term with the accused products' "doorbell" mechanism. (Compl. ¶40). Practitioners may focus on this term because the operational details of a "doorbell" may differ from the specific read-and-decrement functionality described for the "reservation register."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification may describe the register's purpose functionally, as a "shared counter resource" for tracking free space, which could support a broader definition encompassing various hardware synchronization mechanisms. (’596 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The claim language requires that the second processing element "accesses said reservation register and reads said stored value" to determine space. (’596 Patent, col. 11:40-42). This suggests a specific read-based operation, which a defendant might argue is distinct from a write-based doorbell signal.

For the ’753 Patent:

  • The Term: "swappable pods or cards"
  • Context and Importance: This term defines the physical and architectural modularity of the claimed platform. The infringement case depends on the accused AMD Pensando DSC, an industry-standard PCIe card, meeting this definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states that "Pods and cards are removable, insertable, replaceable and optionally hot-swappable in the chassis." (’753 Patent, col. 2:57-59). This functional description could be argued to cover standard form-factor cards like PCIe cards.
    • Evidence for a Narrower Interpretation: The patent's figures consistently depict a blade-server-style architecture with proprietary "pods" sliding into a custom chassis. (’753 Patent, Figs. 1A, 10, 11). A defendant may argue this context limits the claim to such proprietary modular systems, excluding standard PCIe cards installed in general-purpose servers.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all five asserted patents. The inducement claims are based on allegations that Defendants sell the Accused Products and provide documentation, user manuals, and support that encourage and instruct customers on how to use them in an infringing manner. (Compl. ¶¶45, 58, 71, 83, 97).
  • Willful Infringement: The complaint alleges willful infringement of all five patents. The primary basis for this allegation is a June 2014 meeting between AMD and Plaintiffs' commercialization agent, HellaStorm, Inc., under a Mutual Nondisclosure Agreement, where Plaintiffs' technology was allegedly disclosed to AMD. (Compl. ¶30). This alleged pre-suit knowledge, combined with Defendants' failure to cease infringement after the filing of the complaint, forms the basis for willfulness. (Compl. ¶¶31-32).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical mechanism: do the accused DPU's "doorbell" and scheduler systems, which are central to its operation, function in the specific manner required by the '596 patent's "reservation register," which is defined by a distinct read-access-and-decrement sequence?
  • A central dispute will be one of definitional scope: can the term "swappable pods or cards," which is illustrated in the '753 and '943 patents with a proprietary blade-style architecture, be construed to cover industry-standard PCIe cards like the accused AMD Pensando Distributed Services Cards when installed in a general-purpose server chassis?
  • A key evidentiary question will be one of functional implementation: while the accused DPUs are P4-programmable, can Plaintiffs provide evidence that they are configured and operated in a way that actually uses the specific five-part addressing header required by claim 1 of the '753 patent or the network optimization method of the '634 patent?