DCT

1:24-cv-00416

Eireog Innovations Ltd v. Dell Tech Inc

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:24-cv-00416, W.D. Tex., 06/04/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants have regular and established places of business in the Western District of Texas.
  • Core Dispute: Plaintiff alleges that a wide range of Defendant’s computer products, including servers, laptops, and desktops containing certain Intel and AMD processors, infringe five patents related to low-level processor architecture, including interrupt management, cache coherency, and power management.
  • Technical Context: The patents-in-suit address fundamental challenges in modern multi-core and virtualized computing environments, focusing on improving efficiency and performance at the hardware level.
  • Key Procedural History: The complaint is an amended version of an original complaint filed on April 19, 2024. Plaintiff alleges that Defendant has had knowledge of the asserted patents and their alleged infringement at least since this original filing date, which forms the basis for allegations of indirect and willful infringement.

Case Timeline

Date Event
2009-05-07 Priority Date for U.S. Patent No. 8,117,399
2010-09-21 Priority Date for U.S. Patent No. 8,504,777
2010-11-25 Priority Date for U.S. Patent No. 9,335,805
2012-02-14 Issue Date for U.S. Patent No. 8,117,399
2012-08-09 Priority Date for U.S. Patent Nos. 9,436,626 & 9,442,870
2013-06-01 Approximate Launch of Intel Haswell CPUs (Accused Product Line)
2013-08-06 Issue Date for U.S. Patent No. 8,504,777
2015-08-01 Approximate Launch of Intel Skylake CPUs (Accused Product Line)
2016-05-10 Issue Date for U.S. Patent No. 9,335,805
2016-09-06 Issue Date for U.S. Patent No. 9,436,626
2016-09-13 Issue Date for U.S. Patent No. 9,442,870
2021-11-01 Approximate Launch of Intel Alder Lake CPUs (Accused Product Line)
2024-04-19 Original Complaint Filed
2024-06-04 Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements"

  • Patent Identification: U.S. Patent No. 9,436,626, "Processor interrupt interface with interrupt partitioning and virtualization enhancements," issued September 6, 2016.

The Invention Explained

  • Problem Addressed: In complex data processing systems with multiple processors or virtualized partitions, managing and routing interrupt requests can be slow and inefficient, often requiring significant software overhead from a hypervisor to direct interrupts to the correct partition (’626 Patent, col. 1:11-40).
  • The Patented Solution: The patent describes a processor-based interrupt management system where interrupt requests are delivered directly to the processor core along with a package of context information, including a partition ID, thread ID, and priority level. The processor core uses its own special purpose registers to evaluate this information and determine whether to block the interrupt or forward it to the correct virtual processor (thread), reducing latency by minimizing reliance on a separate interrupt controller or hypervisor intervention (’626 Patent, col. 2:15-40).
  • Technical Importance: This hardware-based approach aims to accelerate interrupt handling, a critical function for performance in the highly virtualized and multi-threaded computing environments that dominate modern data centers and high-performance computing (’626 Patent, col. 2:41-45).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶11).
  • The essential elements of independent claim 1, a method claim, include:
    • Receiving, at a processor, an interrupt package for a physical interrupt request.
    • The package comprises an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
    • Processing the package against one or more partitions running on the processor.
    • The processing includes comparing the priority value and partition identifier against stored values in special purpose registers.
    • Determining on a partition basis whether the request is blocked or forwarded to a targeted thread.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers"

  • Patent Identification: U.S. Patent No. 9,442,870, "Interrupt priority management using partition-based priority blocking processor registers," issued September 13, 2016.

The Invention Explained

  • Problem Addressed: The patent identifies performance issues in partitioned systems that arise from accessing and changing interrupt blocking conditions at a central interrupt controller, particularly for virtualized machines (’870 Patent, col. 3:1-10).
  • The Patented Solution: The invention proposes controlling interrupt priority blocking via special purpose registers located directly at the processor core. An interrupt request is presented to the core with a partition identifier (LPID), which is used to select the appropriate on-core priority register (e.g., a hypervisor-level or guest-level register). The interrupt's priority is then compared to the value in that register to determine if it should be blocked or forwarded, allowing for independent priority management by different partitions (’870 Patent, Abstract; col. 2:1-24).
  • Technical Importance: This architecture simplifies the central interrupt controller and empowers individual partitions (like a guest operating system) to manage their own interrupt blocking conditions with low latency, enhancing performance in virtualized environments (’870 Patent, col.4:1-13).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶21).
  • The essential elements of independent claim 1, a method claim, include:
    • Receiving at the processor an interrupt package for a physical interrupt request, comprising a priority value and a partition identifier.
    • Processing the package against partitions running on targeted virtual processors.
    • The processing involves comparing the priority value and partition identifier against a stored priority level and partition identifier retrieved from special purpose registers.
    • Determining on a partition basis if the request is blocked or forwarded.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,504,777 - "Data processor for processing decorated instructions with cache bypass"

  • Patent Identification: U.S. Patent No. 8,504,777, "Data processor for processing decorated instructions with cache bypass," issued August 6, 2013.

Technology Synopsis

The patent addresses the problem of maintaining cache coherency when a processor offloads certain atomic operations (termed "decorated instructions," e.g., read-modify-write) to an intelligent memory device (’777 Patent, col. 2:48-54). Because the processor is unaware of the modification occurring in memory, its own cache can become stale. The solution is to have the processor bypass its cache for these specific instructions; if a decorated instruction results in a cache hit, the corresponding cache entry is flushed and invalidated to force a fresh read from memory (’777 Patent, col. 2:54-67).

Asserted Claims

The complaint asserts independent claim 16 (Compl. ¶31).

Accused Features

The complaint alleges that the cache processing features of Dell products containing Intel CPUs (Skylake and newer) and AMD EPYC CPUs infringe the ’777 Patent (Compl. ¶30, ¶34).

U.S. Patent No. 8,117,399 - "Processing of coherent and incoherent accesses at a uniform cache"

  • Patent Identification: U.S. Patent No. 8,117,399, "Processing of coherent and incoherent accesses at a uniform cache," issued February 14, 2012.

Technology Synopsis

The patent seeks to reduce interconnect congestion in multi-core processors caused by cache coherency "snoop" traffic (’399 Patent, col. 1:19-24). It proposes a unified cache where each cache line is marked as either "coherent" (e.g., for shared data) or "incoherent" (e.g., for non-modified instruction code). An incoherent read that misses the cache can be resolved with a "non-global snoop" to a limited set of targets, reducing traffic. A coherent read that hits an "incoherent" line is treated as a miss, forcing a "global snoop" to ensure the processor has the most up-to-date data, thus maintaining coherency where it matters (’399 Patent, Abstract).

Asserted Claims

The complaint asserts independent claim 14 (Compl. ¶41).

Accused Features

The complaint alleges that the cache processing and coherency features of Dell products containing Intel CPUs (Skylake and newer) and AMD EPYC CPUs infringe the ’399 Patent (Compl. ¶40, ¶44).

U.S. Patent No. 9,335,805 - "Method and apparatus for managing power in a multi-core processor"

  • Patent Identification: U.S. Patent No. 9,335,805, "Method and apparatus for managing power in a multi-core processor," issued May 10, 2016.

Technology Synopsis

The patent describes a power management method for multi-core processors that adapts to workload characteristics. It determines the "split-ability" (parallelism) of an application, as well as the processor's thermal state and leakage currents (’805 Patent, col. 6:42-50). Based on these factors, it decides whether it is more power-efficient to run a workload on a single core at high frequency or on multiple cores at a lower frequency. For instance, for a high-leakage processor or a low-parallelism workload, the system may transition to a single high-performance core to save power (’805 Patent, col. 7:1-9).

Asserted Claims

The complaint asserts independent claim 6 (Compl. ¶51).

Accused Features

The complaint alleges that the power management features of Dell products containing Intel Core CPUs (12th Generation Alder Lake and newer) infringe the ’805 Patent (Compl. ¶50, ¶54).

III. The Accused Instrumentality

Product Identification

The complaint identifies a broad and extensive list of "Accused Products," including Dell's PowerEdge Tower and Rack Servers, PowerStore storage, VXRail hyper-converged systems, and numerous product lines of workstations, desktops, and laptops, such as Precision, XPS, Alienware, Latitude, and Inspiron (Compl. ¶10, ¶20, ¶30, ¶40, ¶50).

Functionality and Market Context

The core of the infringement allegations is not the end-products themselves, but the CPUs they incorporate, specifically Intel processors from the Haswell, Skylake, and Alder Lake generations (and newer) and various AMD Zen-based processors (Compl. ¶10, ¶30, ¶40, ¶50). The complaint alleges that the infringing functionality is embedded within the CPU's hardware architecture for managing interrupts, cache coherency, and power. The complaint references Dell's marketing materials to assert the commercial importance of these processors and their features to the functionality of the Accused Products (Compl. ¶13, ¶23).

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits that would detail the infringement allegations on an element-by-element basis (Compl. ¶11, ¶21). The infringement theories are therefore summarized below in prose based on the complaint's narrative allegations. No probative visual evidence provided in complaint.

  • ’626 Patent Infringement Allegations: The complaint alleges that the Accused Products, by incorporating certain Intel and AMD CPUs, directly infringe claim 1 of the ’626 Patent (Compl. ¶10-11). The narrative theory is that these modern CPUs, operating in virtualized environments, inherently perform the patented method. They are alleged to feature on-core hardware that receives and processes interrupt requests packaged with partition and priority information, using this data to manage interrupt blocking and routing to specific virtual cores or threads without relying on slower, off-core mechanisms (Compl. ¶10, ¶13).

  • ’870 Patent Infringement Allegations: The infringement theory for the ’870 Patent is substantively similar to that for the ’626 Patent. The complaint alleges that the Accused Products, via their CPUs, infringe claim 1 by using partition-based priority blocking registers located on the processor core (Compl. ¶20-21). These on-core registers are allegedly used to compare the priority level and partition ID of an incoming interrupt request against stored values, thereby enabling different partitions (e.g., a hypervisor and a guest OS) to manage their own interrupt priorities independently and efficiently (Compl. ¶20, ¶23).

  • Identified Points of Contention:

    • Scope Questions: A primary question for the court will be whether the functionality of industry-standard processor components, such as Intel's Advanced Programmable Interrupt Controller (APIC), falls within the scope of the patents' claims for "special purpose registers" and an "interrupt package." The defense may argue that the accused CPUs implement these functions using a different, non-infringing architecture, raising a central dispute over claim construction and technical equivalence.
    • Technical Questions: The complaint asserts that the accused CPUs perform the claimed methods but provides no specific public evidence detailing how these proprietary, internal operations occur. A key evidentiary question will be whether discovery reveals that the accused CPUs' hardware actually receives interrupt information as a discrete "package" and uses on-core registers for partition-based blocking in the specific manner required by the claims.

V. Key Claim Terms for Construction

  • The Term: "special purpose register" (in claims of ’626 and ’870 patents)

    • Context and Importance: This term is central to the claimed invention, which moves interrupt-blocking logic from a general controller onto the processor core itself via these registers. The infringement analysis for the '626 and '870 patents will depend heavily on whether the hardware structures within the accused CPUs are construed as "special purpose registers."
    • Intrinsic Evidence for a Broader Interpretation: Plaintiff may argue the term should be interpreted functionally to cover any on-core register or hardware logic that stores partition and priority information for the purpose of managing interrupts, as described in the specification (’626 Patent, col. 2:50-60).
    • Intrinsic Evidence for a Narrower Interpretation: The patents provide specific examples of these registers, such as the "LPIDR", "EPR", and "INTLEVEL" registers (’626 Patent, Fig. 2; ’870 Patent, Fig. 3). Defendant may argue that the term should be limited to such explicitly named or structured registers and not read on more general interrupt-handling architectures.

  • The Term: "interrupt package" (in claim 1 of the ’626 patent)

    • Context and Importance: Claim 1 requires "receiving... an interrupt package" containing a list of five distinct identifiers (request, interrupt ID, partition ID, priority value, thread ID). Infringement requires showing that the accused CPUs receive this information as a "package."
    • Intrinsic Evidence for a Broader Interpretation: Plaintiff may argue that a "package" refers to the collection of all necessary context information that is made available to the processor for evaluation, not necessarily a single, monolithic data transmission.
    • Intrinsic Evidence for a Narrower Interpretation: Defendant may argue that the term, particularly with the specification's description of information being "delivered directly with the interrupt request" (’626 Patent, col. 2:20-22), requires a discrete data structure containing all the recited elements. If the accused CPUs gather this information from different sources or through multiple steps, it may not meet this narrower construction.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement under 35 U.S.C. § 271(b). The allegations are based on Dell providing "user manuals and online instruction materials" that allegedly instruct customers to configure and use the Accused Products in a manner that directly infringes the patents (e.g., by utilizing their virtualization, cache, and power management functionalities) (Compl. ¶13, ¶23, ¶33, ¶43, ¶53).
  • Willful Infringement: The complaint alleges that Dell gained knowledge of the asserted patents and its alleged infringement "at least as of the filing and service of the original complaint on April 19, 2024," which included claim charts (Compl. ¶13, ¶23, ¶33, ¶43, ¶53). By alleging that Dell continued its infringing conduct despite this knowledge, the complaint lays the groundwork for a claim of post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of architectural equivalence: can the specific methods and structures described in the patents, which appear to be novel architectural proposals, be read to cover the functionality of widely adopted, complex, and potentially distinct architectures developed by major CPU manufacturers like Intel and AMD?
  • The case will also turn on a question of definitional scope: the construction of fundamental claim terms such as "special purpose register," "interrupt package," and "decorated instruction" will be dispositive. The central dispute will be whether these terms are broad enough to encompass the functions of the accused processors or are limited to the specific embodiments disclosed in the patents.
  • Finally, a key challenge for the plaintiff will be one of evidentiary proof: the complaint relies on high-level functional allegations. The case will likely depend on what evidence can be compelled through discovery to demonstrate that the proprietary, internal workings of the accused CPUs perform the patented methods as claimed.