Eireog Innovations Ltd v. HP Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Eireog Innovations Ltd. (Ireland)
  • Defendant: HP Inc. (Delaware)
  • Plaintiff’s Counsel: BC LAW GROUP, Group
• Case Identification: 1:24-cv-00644, W.D. Tex., 08/13/2024
• Venue Allegations: Plaintiff alleges venue is proper because HP is registered to do business in Texas, has transacted business and committed acts of infringement in the district, and maintains a regular and established place of business in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant’s computer products incorporating certain Intel and AMD multi-core processors infringe two patents related to managing processor interrupts in partitioned and virtualized environments.
• Technical Context: The technology concerns methods for efficiently handling and prioritizing interrupt requests in multi-core processors, a foundational element for performance and stability in modern computing systems from consumer laptops to enterprise servers.
• Key Procedural History: The filing is an Amended Complaint, which states that an original complaint and associated claim charts were previously served on the Defendant. This prior notice forms the basis of Plaintiff’s allegations regarding Defendant’s knowledge of the patents and the alleged infringement.

Case Timeline

Date	Event
2012-08-09	Priority Date for '626 and '870 Patents
2016-09-06	U.S. Patent No. 9,436,626 Issued
2016-09-13	U.S. Patent No. 9,442,870 Issued
2024-08-13	Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements"

• Patent Identification: U.S. Patent No. 9,436,626, titled "Processor interrupt interface with interrupt partitioning and virtualization enhancements," issued on September 6, 2016. (Compl. ¶8).

The Invention Explained

• Problem Addressed: The patent describes performance bottlenecks in multi-processor systems where multiple processors compete for access to a memory-mapped interrupt controller. This issue is exacerbated in partitioned or virtualized systems, where routing interrupts to the correct virtual machine or partition adds software complexity and latency. (’626 Patent, col. 1:13-39).
• The Patented Solution: The invention proposes moving the interrupt management logic from a centralized controller directly into the processor core itself. The system delivers an interrupt request along with associated context—such as a partition ID, thread ID, and priority level—to the processor core. The core then uses its own "special purpose registers" to evaluate this context and determine, on a partition-by-partition basis, whether to accept or block the interrupt, thereby reducing software overhead and access delays to an external controller. (’626 Patent, Abstract; col. 2:16-46; Fig. 2).
• Technical Importance: This architecture aims to provide a lower-latency, hardware-based method for managing interrupts in complex virtualized environments, a critical factor for improving performance and responsiveness. (’626 Patent, col. 2:25-34).

Key Claims at a Glance

• The complaint asserts independent claim 1 and reserves the right to assert additional claims. (Compl. ¶10).
• The essential elements of independent claim 1 include:
  • Receiving at a processor an "interrupt package" from an interrupt controller.
  • The package comprising a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
  • Processing the package by comparing the priority value and partition identifier against a stored priority level and partition identifier retrieved from "special purpose registers at the processor."
  • Determining, on a partition basis, whether the interrupt request is blocked or forwarded to a targeted thread.

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers"

• Patent Identification: U.S. Patent No. 9,442,870, titled "Interrupt priority management using partition-based priority blocking processor registers," issued on September 13, 2016. (Compl. ¶18).

The Invention Explained

• Problem Addressed: The patent identifies the same technical problem as its related '626 Patent: performance degradation and complexity in managing interrupt priority in multi-core, virtualized systems due to reliance on a centralized interrupt controller. (’870 Patent, col. 1:15-24).
• The Patented Solution: The invention describes a processor core architecture that includes special purpose priority blocking registers (e.g., INTLEVEL, GINTLEVEL). When an interrupt request arrives with a partition identifier (LPID) and priority level, the processor core itself compares these values to the levels stored in its own registers. This allows the core to manage interrupt blocking for different partitions (such as a hypervisor and guest operating systems) directly in hardware, without needing to access an external controller for the decision. (’870 Patent, Abstract; col. 2:1-21; Fig. 2).
• Technical Importance: By embedding partition-aware priority-blocking logic into the processor core, the invention seeks to create a more efficient and responsive interrupt handling system for virtualized environments. (’870 Patent, col. 2:22-39).

Key Claims at a Glance

• The complaint asserts independent claim 1 and reserves the right to assert additional claims. (Compl. ¶20).
• The essential elements of independent claim 1 include:
  • Receiving at the processor an "interrupt package" containing a first priority value and a first partition identifier.
  • Processing the package by comparing the priority and partition identifiers against a stored priority level and partition identifier from "one or more special purpose registers at the processor."
  • Determining on a partition basis whether the physical interrupt request is blocked or forwarded to a targeted virtual processor.

III. The Accused Instrumentality

Product Identification

The complaint identifies a wide range of HP computer products, including but not limited to laptops, desktops, and workstations from its Envy, Pavilion, Omen, EliteBook, and ZBook lines, which incorporate "Intel-based CPUs (Haswell-based architecture and newer)" or "AMD Zen-based CPUs" (collectively, the "Accused Products"). (Compl. ¶¶9, 19).

Functionality and Market Context

The infringement allegations focus on the interrupt management functionalities within the Intel and AMD processors contained in the Accused Products. (Compl. ¶¶13, 23). The complaint alleges that HP markets and sells these products, advertising the benefits of the accused processors, and provides user manuals and instructions that encourage use of the allegedly infringing functionality. (Compl. ¶¶12, 22).

• No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits that detail its infringement theories. (Compl. ¶¶10, 20). The narrative allegations state that the Accused Products, by virtue of containing the specified Intel and AMD processors, practice all limitations of at least claim 1 of each of the asserted patents. (Compl. ¶¶10, 20). The core of the infringement allegation is that the interrupt management and virtualization features of these modern CPUs perform the patented methods of using on-core registers to manage interrupt priority and routing on a partition-specific basis.

• Identified Points of Contention:
  • Architectural Equivalence: A primary point of contention may be whether the architecture of the accused Intel and AMD processors maps onto the specific "partition-based" system claimed in the patents. The dispute may center on whether the processors' mechanisms for handling virtualization (e.g., Intel VT-x, AMD-V) and interrupts are architecturally equivalent to the "special purpose registers" and "partition identifiers" described in the patents, or if they represent a distinct, non-infringing approach.
  • Location of Functionality: The patents claim a system where interrupt-blocking decisions are made "at the processor" using its own registers. A technical question will be what level of involvement, if any, a hypervisor or system software has in the process on the accused devices. The defense may argue that the functionality is not performed in the specific hardware-centric manner required by the claims.

V. Key Claim Terms for Construction

• The Term: "special purpose registers at the processor" (appears in claim 1 of both the '626 and '870 Patents)

  • Context and Importance: This term is central to the claimed invention, which locates the novel interrupt-blocking logic in these specific registers. Infringement will likely depend on whether the registers within the accused Intel and AMD CPUs that handle interrupt and virtualization tasks are construed as "special purpose registers" for partition-based interrupt management.
  • Intrinsic Evidence for a Broader Interpretation: The specification describes the function of these registers as evaluating "partition ownership information, priority, and interrupt IDs delivered directly with the interrupt request." (’626 Patent, col. 2:19-22). A plaintiff may argue that any register or set of registers within the processor core that performs this specific function is a "special purpose register," irrespective of its name or other potential uses.
  • Intrinsic Evidence for a Narrower Interpretation: The specification provides specific examples of these registers, such as the LPIDR, INTLEVEL, EPR, and EPIDR. (’626 Patent, Fig. 2; ’870 Patent, Fig. 2). A defendant may argue that the term should be limited to registers that correspond closely to these disclosed embodiments and their described interactions, asserting that they represent the actual invention.

• The Term: "partition identifier" (appears in claim 1 of both the '626 and '870 Patents)

  • Context and Importance: The "partition-based" nature of the claims hinges on this term. The dispute will concern what data within the accused systems constitutes a "partition identifier."
  • Intrinsic Evidence for a Broader Interpretation: The specification explains that the conveyed "LPID data is used to direct the interrupt to the recipient partition." (’626 Patent, col. 6:5-7). This functional description could support an argument that any data that uniquely identifies a target virtual machine or partition for an interrupt—such as a VMID used in modern virtualization technologies—falls within the scope of the term.
  • Intrinsic Evidence for a Narrower Interpretation: The patent consistently refers to a "logical partition identifier (LPID)" and describes its use in a specific interrupt-handling context. (’626 Patent, col. 5:26-28). A defendant could argue that this consistent usage limits the term to an explicit identifier configured for the claimed interrupt management scheme, as distinguished from more general-purpose identifiers used in virtualization.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement. Inducement is based on allegations that HP, with knowledge of the patents, provides user manuals and instructions that direct customers to use the accused products in an infringing manner. (Compl. ¶¶12, 22). Contributory infringement is based on allegations that the processors' interrupt management features are a material part of the invention, are especially adapted for infringement, and are not staple articles of commerce. (Compl. ¶¶13, 23).
• Willful Infringement: The complaint alleges that HP has had knowledge of the patents and its infringement "At least as of the filing and service of the original complaint" and associated claim charts. (Compl. ¶¶12, 22). Continued alleged infringement after this date forms the basis for a potential claim of post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of claim scope and technical interpretation: Can the terms "special purpose registers" and "partition identifier," as defined by the patents, be construed to read on the specific hardware registers and data structures (e.g., VM-control structures, APIC registers) used by the accused Intel and AMD processors for virtualization and interrupt management, or is there a fundamental architectural mismatch?
• A key evidentiary question will be one of operational proof: What evidence will be presented to demonstrate that the accused processors perform the specific multi-step "comparing" and "determining" functions as recited in the claims entirely within the processor core, as opposed to a different method that relies more heavily on a hypervisor or other system software for managing interrupt blocking and routing?