DCT

1:25-cv-00358

MOSAID Tech Inc v. Infineon Tech AG

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00358, W.D. Tex., 03/10/2025
  • Venue Allegations: Venue is alleged to be proper for Infineon Technologies AG as a foreign corporation subject to personal jurisdiction in the district, and for Infineon Technologies Americas Corp. based on its regular and established place of business in Austin, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s Programmable System-on-Chip (PSoC) and wireless connectivity System-on-Chip (SoC) products infringe patents related to dynamic power management, power island control, and distributed multiplexing circuit design.
  • Technical Context: The lawsuit concerns fundamental technologies for managing power consumption and data routing within complex semiconductor chips, which are critical for balancing performance against battery life in a wide range of modern electronic devices.
  • Key Procedural History: The complaint alleges a long history of pre-suit licensing discussions, initiated by Plaintiff with Cypress Semiconductor in November 2017. These discussions, which included the exchange of claim charts for the asserted patents, allegedly continued after Infineon acquired Cypress in April 2020. Plaintiff claims that its recent efforts to resolve the matter and offer a license were ignored by Infineon, forming the basis for allegations of willful infringement.

Case Timeline

Date Event
2001-10-11 U.S. Patent No. 7,111,179 Priority Date
2003-05-07 U.S. Patent No. 7,051,306 Priority Date
2003-08-01 U.S. Patent No. 7,349,448 Priority Date
2006-05-23 U.S. Patent No. 7,051,306 Issue Date
2006-09-19 U.S. Patent No. 7,111,179 Issue Date
2008-03-25 U.S. Patent No. 7,349,448 Issue Date
2017-11-03 Plaintiff (MOSAID) allegedly sent letter and claim charts to Cypress Semiconductor
2020-04-16 Infineon allegedly acquired Cypress Semiconductor
2025-03-10 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,111,179 - "Method and Apparatus for Optimizing Performance and Battery Life of Electronic Devices Based on System and Application Parameters"

  • Patent Identification: U.S. Patent No. 7,111,179, "Method and Apparatus for Optimizing Performance and Battery Life of Electronic Devices Based on System and Application Parameters," issued September 19, 2006 (Compl. ¶44).

The Invention Explained

  • Problem Addressed: The patent addresses the growing gap between the processing power of portable electronics and their limited battery life. It notes that prior art power-saving techniques were often simplistic, relying on individual parameters or basic thresholds, which could lead to power-saving states being entered at "inopportune time[s]" that "adversely affect performance" (Compl. ¶51; ’179 Patent, col. 2:21-24).
  • The Patented Solution: The invention proposes a more sophisticated dynamic power management system. It samples a plurality of different parameters (e.g., microprocessor, OS, peripheral, and environmental events), normalizes their values, and mathematically combines them through a series of successive stages to produce a single, comprehensive "overall parameter value." This value is then used to intelligently adjust run-time parameters like microprocessor clock frequency and voltage, aiming to reduce power consumption without a noticeable impact on user experience (Compl. ¶¶48-49; ’179 Patent, Abstract; Fig. 6).
  • Technical Importance: The technology represents a shift toward a holistic, multi-factor approach to power management, allowing for more nuanced control than was possible with earlier methods that monitored fewer, less-diverse system parameters (Compl. ¶52; ’179 Patent, col. 2:31-41).

Key Claims at a Glance

  • The complaint asserts at least independent Claim 1 (Compl. ¶96).
  • The essential elements of Claim 1 are:
    • A system for dynamically managing power within an electronic device, comprising a power management device.
    • A "sampling module" to ascertain and store a plurality of parameter values.
    • An "analysis module" to combine the parameter values to produce an overall parameter value, where the parameters are arranged into a "series of successive stages".
    • The analysis module includes a "normalization module" to normalize parameter values and a "combination module" to mathematically combine normalized parameters from a subordinate stage with a succeeding stage.
    • An "adjustment module" to adjust the electronic device's power consumption based on a control value derived from the overall parameter value.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,051,306 - "Managing Power on Integrated Circuits Using Power Islands"

  • Patent Identification: U.S. Patent No. 7,051,306, "Managing Power on Integrated Circuits Using Power Islands," issued May 23, 2006 (Compl. ¶54).

The Invention Explained

  • Problem Addressed: The patent identifies inefficiencies in prior art integrated circuits where power consumption was not managed dynamically or granularly. For example, an entire chip might operate at maximum frequency for the benefit of a single component, and the voltages and clock frequencies within power islands were often static, failing to adapt to the changing operational needs of the circuit (Compl. ¶¶60-61; ’306 Patent, col. 2:10-17).
  • The Patented Solution: The invention describes a system that uses distinct "power islands" on an integrated circuit, where power consumption can be independently and dynamically controlled. A "power manager" determines a target power level for a specific island based on the needs and operation of the circuit. The manager then performs an action—such as selecting a clock frequency, modifying a voltage, or powering the island on or off—to adjust the island's power consumption to the target level (Compl. ¶58; ’306 Patent, Abstract; col. 4:18-34).
  • Technical Importance: This approach allows for fine-grained, dynamic power control over different functional blocks of a complex System-on-a-Chip, improving overall power efficiency compared to systems with static power domains or chip-wide power settings (Compl. ¶61).

Key Claims at a Glance

  • The complaint asserts at least independent Claim 16 (Compl. ¶126).
  • The essential elements of Claim 16 are:
    • A system for an integrated circuit comprising a "plurality of power islands" where power consumption is independently controlled.
    • "Power control circuitry" configured to control power for one of the power islands.
    • A "power manager" configured to determine a target power level for an island, determine an action to change the power consumption to that level, and perform the action, where one of the actions comprises "selecting a frequency" for the power island.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,349,448 - "Distributed Multiplexing Circuit with Built-In Repeater"

  • Patent Identification: U.S. Patent No. 7,349,448, "Distributed Multiplexing Circuit with Built-In Repeater," issued March 25, 2008 (Compl. ¶63).
  • Technology Synopsis: The patent addresses the problem of routing congestion on integrated circuits caused by wide data buses being routed to a central multiplexer (MUX). The invention discloses a distributed MUX architecture where logic is arranged in stages. Each stage selects between a local data input and a data word from a previous stage, and this staged design also serves to boost signal strength, acting as a built-in repeater for signals traveling long distances across the chip (Compl. ¶¶68-70).
  • Asserted Claims: The complaint asserts at least independent Claim 4 (Compl. ¶156).
  • Accused Features: The PSoC 5LP family of processors is accused. The complaint alleges that the on-chip bus matrix architecture, which manages data flow between components like the CPU and memory, functions as the claimed multi-stage multiplexer circuit (Compl. ¶¶159, 162).

III. The Accused Instrumentality

Product Identification

  • The "Accused Products" include specific families of Infineon's semiconductor products, namely the PSoC 3, PSoC 4, PSoC 5, and PSoC 6 families of Programmable System-on-Chip (PSoC) products, as well as the AIROC Wi-Fi and Bluetooth Combo products (Compl. ¶¶15, 89).

Functionality and Market Context

  • These products are highly integrated microcontrollers (MCUs) and Systems-on-a-Chip (SoCs) that combine processor cores with programmable analog and digital blocks, memory, and various peripherals on a single chip (Compl. ¶¶15, 34).
  • The PSoC products are marketed for a wide array of applications, including consumer electronics, Internet of Things (IoT), automotive, and industrial control systems (Compl. ¶¶14, 89). The complaint alleges these products are widely available for sale in the U.S. and in the Western District of Texas through Infineon's website and distribution partners (Compl. ¶¶16, 19). The complaint provides screenshots from Infineon's website showing various PSoC and AIROC products available for purchase (Compl. ¶16, pp. 4-6).
  • The complaint highlights the commercial importance of these products, noting their use in Tesla vehicles, their integration into wireless charging modules for industrial machinery, and the operation of a major manufacturing facility ("Fab25") in Austin, Texas, that produces over a billion chips per year, including some of the Accused Products (Compl. ¶¶21, 22, 34).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,111,179 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a sampling module to ascertain and store a plurality of parameter values associated with said electronic device during at least one sampling interval The "Power Monitor" component in PSoC 3, 4, and 5 is configured to measure power converter output voltages and supports averaging of voltage and current measurements, calculated as a running average over N scans. ¶100 col. 10:48-54
an analysis module to combine said plurality of parameter values to produce an overall parameter value... wherein said plurality of parameters are arranged into a series of successive stages The Power Monitor combines the sampled voltage parameter values into an overall running average, which is used to evaluate fault and warning thresholds. The complaint states the parameters are arranged into successive stages. ¶101 col. 10:30-40
a normalization module to normalize said parameter values relative to a numeric range The accused PSoC products can be configured with a "voltage scaling factor" that controls attenuation applied to the converter output voltage. A screenshot from a PSoC Creator datasheet shows a configurable "Input scaling factor" for power converters (Compl. p. 28). ¶102 col. 8:52-59
a combination module to mathematically combine said normalized parameters of each subordinate stage with a succeeding stage to produce an overall value The PSoC 3, 4, and 5 allegedly combine the normalized voltage values as a running average to use when evaluating fault or warning conditions. ¶103 col. 8:1-12
an adjustment module to adjust power consumption of said electronic device The accused products include a voltage sequencer, connectable to the Power Monitor, that supports sequencing and monitoring of up to 32 power converter rails. ¶104 col. 10:40-47
  • Identified Points of Contention:
    • Scope Questions: The primary question is whether the accused "Power Monitor," which calculates a "running average" of voltage values, meets the "series of successive stages" limitation. The patent specification appears to describe a more complex, hierarchical combination of diverse parameter types ('179 Patent, Fig. 6), raising the question of whether a simple running average of a single parameter type falls within the claim's scope.
    • Technical Questions: What evidence demonstrates that the accused "voltage scaling factor" performs the function of normalizing a parameter value "relative to a numeric range" as required by the claim? The infringement analysis may depend on whether this scaling operation is functionally equivalent to the normalization described in the patent.

U.S. Patent No. 7,051,306 Infringement Allegations

Claim Element (from Independent Claim 16) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for an integrated circuit comprising a plurality of power islands where power consumption is independently controlled within each of the power islands The PSoC 6 MCU architecture includes multiple independently controlled subsystems, such as the Cortex M-4 and M-0+ CPU cores (which can sleep independently), a Bluetooth subsystem, and programmable analog/digital blocks, which function as power islands. A block diagram from an Infineon manual illustrates these distinct functional domains (Compl. p. 39). ¶¶129-130 col. 4:50-54
power control circuitry configured to control power for one of the power islands The PSoC 63 line includes circuitry for enabling and disabling clocks to peripherals, powering clock sources on/off, and powering peripherals on/off. ¶131 col. 4:5-13
a power manager configured to determine a target power level... determine at least one of actions... and perform the at least one of the actions... where one of the actions comprises selecting a frequency for the one of the power islands The accused PSoC 6 and AIROC products allegedly use firmware to function as a power manager. This firmware decides when to enable or disable peripherals and power domains based on application requirements. The products support dynamic voltage and frequency scaling, and the firmware adjusts the frequency when transitioning between power states (e.g., Active, Sleep, Deep-Sleep). A power mode transition diagram shows firmware actions causing these state changes (Compl. p. 40). ¶¶132-133 col. 4:18-34
  • Identified Points of Contention:
    • Scope Questions: A central dispute may be whether the accused "firmware" that manages power modes (Compl. ¶132) constitutes the claimed "power manager." The defense could argue this is standard functionality of an operating system or driver, whereas the patent's specification describes a more structured power management hierarchy (e.g., Master/Slave Power Managers), potentially supporting a narrower construction of the term.
    • Technical Questions: What specific logic or code within the accused firmware performs the claimed function of "determin[ing] a target power level"? The complaint alleges the firmware "may decide to enable or disable specific peripherals," which raises an evidentiary question about how a specific target level is determined and acted upon, as opposed to simply reacting to system events.

V. Key Claim Terms for Construction

For the ’179 Patent:

  • The Term: "series of successive stages" (Claim 1)
  • Context and Importance: This term is central to the infringement analysis, as it defines the structure of the claimed analysis module. The dispute will likely focus on whether the accused "running average" calculation constitutes a "series of successive stages." Practitioners may focus on this term because the patent's embodiment appears more complex than the accused functionality.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A plaintiff may argue that any multi-step computational process, including the iterative calculation of a running average where a new value is combined with a historical value, constitutes a "series of successive stages." The claim language itself does not specify the complexity or nature of the stages.
    • Evidence for a Narrower Interpretation: The specification describes and depicts a hierarchical, tree-like structure where different types of parameters are combined at various levels or "stages" to produce the final overall value (’179 Patent, Fig. 6; col. 8:1-51). A defendant could argue this specific embodiment limits the term to a more complex structure than a simple running average of a single parameter type.

For the ’306 Patent:

  • The Term: "power manager" (Claim 16)
  • Context and Importance: The identity and structure of the "power manager" is critical. The complaint identifies on-chip "firmware" as the power manager. The case may turn on whether this general firmware meets the requirements of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent defines a power manager by its function: circuitry, device, or system configured to determine a target power level and perform an action to achieve it (’306 Patent, col. 4:18-25). A plaintiff will argue that any component, including firmware, that performs these functions meets the definition, regardless of its implementation details.
    • Evidence for a Narrower Interpretation: The detailed description discloses a specific hierarchical architecture comprising a Master Power Manager (MPM), Intermediate Power Managers (IPMs), and Slave Power Managers (SPMs) (’306 Patent, Fig. 2; col. 5:43-52). A defendant may argue that these disclosures limit the term "power manager" to a system with a more defined and specialized structure than general-purpose firmware that handles power states as part of its broader duties.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, stating that Infineon provides its customers with the accused chips along with extensive documentation (datasheets, user manuals, application notes), development tools (APIs, sample source code), and technical support, which allegedly instruct and encourage customers to use the products in an infringing manner (Compl. ¶¶106-111, 136-140, 167-172). Contributory infringement is also alleged on the basis that the accused products are especially made to practice the inventions and are not staple articles of commerce with substantial non-infringing uses (Compl. ¶¶117-118, 148, 180).
  • Willful Infringement: The complaint alleges willful infringement for all three patents. The allegations are grounded in a detailed history of pre-suit notice, beginning with communications from Plaintiff to Infineon's predecessor, Cypress, on November 3, 2017. The complaint alleges that these communications included claim charts for the asserted patents and that discussions continued after Infineon's acquisition of Cypress in April 2020. Plaintiff claims that despite this alleged actual and long-standing knowledge, Infineon continued its infringing conduct and ignored recent attempts to license the portfolio (Compl. ¶¶121-124, 151-154, 183-186).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope and technical mapping: for the '179 patent, can the accused "running average" of a single parameter type be construed to meet the "series of successive stages" limitation, which the patent specification illustrates with a more complex, multi-parameter hierarchy? Similarly, for the '306 patent, does general-purpose firmware that manages power states qualify as the claimed "power manager," or does the patent's disclosure of a specific master/slave architecture require a more specialized component?
  • A second key question will be evidentiary and related to willfulness: given the extensive pre-suit history alleged in the complaint, the focus will be on the specific content of the communications between the parties and whether Infineon's actions post-notice were objectively reckless. The resolution of this issue will depend heavily on discovery into what Infineon knew about the patents and when, and what, if any, good-faith beliefs of non-infringement or invalidity it developed.