Siliconarts Technology US Inc v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Siliconarts Technology US Inc (Texas)
  • Defendant: NVIDIA Corp (Delaware); NVIDIA Singapore Pte. Ltd. (Singapore)
  • Plaintiff’s Counsel: Ciccarelli Law Firm; Winstead
• Case Identification: 1:25-cv-00431, W.D. Tex., 05/16/2025
• Venue Allegations: Venue is alleged to be proper over NVIDIA Corp Corporation because it has a regular and established place of business in the Western District of Texas. Venue over NVIDIA Singapore Pte. Ltd. is based on its status as a foreign defendant.
• Core Dispute: Plaintiff alleges that Defendant’s Graphics Processing Units (GPUs) with dedicated RT Cores infringe patents related to hardware-accelerated, real-time ray tracing architectures.
• Technical Context: The technology involves specialized hardware architectures for real-time ray tracing, a computationally intensive graphics rendering technique that produces highly realistic lighting, shadows, and reflections, which is critical for modern video games and professional visualization.
• Key Procedural History: This First Amended Complaint follows an original complaint. The parties have stipulated that allegations of pre-suit indirect infringement and pre-suit willful infringement of the ’889 Patent are dismissed without prejudice, pending further fact discovery. The complaint also notes prior litigation in the district where NVIDIA Corporation has previously admitted to personal jurisdiction.

Case Timeline

Date	Event
2009-05-28	Earliest Priority Date for ’889 and ’739 Patents
2016-04-12	U.S. Patent No. 9,311,739 Issued
2018-05-08	U.S. Patent No. 9,965,889 Issued
2025-05-16	First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,965,889 - "Ray Tracing Core and Ray Tracing Chip Having the Same" (Issued May 8, 2018)

The Invention Explained

• Problem Addressed: The patent describes that traditional 3-D graphics technology, particularly ray tracing, requires a separate, high-performance processor due to a large amount of computation, leading to performance bottlenecks ('889 Patent, col. 1:16-25). The complaint elaborates that these issues include pipeline stall time from cache memory misses, latency, and inefficient hardware utilization (Compl. ¶¶87, 91).
• The Patented Solution: The invention is a hardware-based ray tracing core designed for efficiency. It proposes a parallel processing architecture using multiple Traversal & Intersection (T&I) units with a Multiple Instruction stream Multiple Data stream (MIMD) design to process different rays concurrently ('889 Patent, Abstract). To address memory latency, it discloses a two-level cache hierarchy (L1 and L2) with a specific bypass and queuing mechanism using First-In, First-Out (FIFO) buffers to mitigate performance penalties from cache misses ('889 Patent, col. 9:14-29; FIG. 8).
• Technical Importance: This type of hardware acceleration architecture is designed to make computationally expensive, high-fidelity ray tracing practical for real-time applications like video games, which was previously limited to offline rendering for cinema (Compl. ¶¶83-85).

Key Claims at a Glance

• The complaint asserts at least Independent Claim 1 (Compl. ¶105).
• Essential elements of Claim 1 include:
  • A ray generation unit configured to generate an eye ray and a shading ray, with shading information having priority over eye ray generation information.
  • A plurality of T&I units with MIMD architecture, each configured to independently and concurrently process a ray.
  • Logic to generate a secondary ray or a shadow ray based on material information at a ray-triangle hit point.
  • Each T&I unit includes an L1 cache, and the core includes a common L2 cache for the L1 caches.
  • A specific cache-miss handling mechanism where, upon an L1 miss, a requirement for L2 access is input to an L1 Address FIFO, and upon an L2 hit, an address and data are input to an L1 Address/Data FIFO.
• The complaint does not explicitly reserve the right to assert dependent claims but incorporates all preceding paragraphs into its infringement count (Compl. ¶104).

U.S. Patent No. 9,311,739 - "Ray Tracing Core and Ray Tracing Chip Having the Same" (Issued April 12, 2016)

The Invention Explained

• Problem Addressed: The patent addresses the same fundamental problem as the ’889 Patent: the high computational cost and architectural inefficiencies of traditional ray tracing that limit its use in real-time applications ('739 Patent, col. 1:16-25; Compl. ¶87).
• The Patented Solution: This patent also describes a specialized ray tracing core. Its key features include a unified single pipeline architecture for traversal and intersection tests, which aims to eliminate inefficiencies like load imbalances found in separate hardware pipelines (Compl. ¶88; '739 Patent, col. 8:46-54). A central feature is the management of multiple ray types (eye, shadow, secondary) and the use of a "secondary ray stack" to manage recursive rays. The ray generation unit is configured to push secondary rays onto the stack and later pop them for processing when a "null ray" is encountered, indicating the termination of a prior ray path ('739 Patent, col. 4:36-58).
• Technical Importance: The disclosed architecture with its unified pipeline and ray stack management claims to reduce processing bottlenecks and more efficiently handle the complex, recursive nature of ray tracing calculations (Compl. ¶¶88, 90).

Key Claims at a Glance

• The complaint asserts at least Independent Claim 1 (Compl. ¶153).
• Essential elements of Claim 1 include:
  • A ray generation unit that distinguishes between eye, shadow, and secondary ray types.
  • A plurality of T&I units with MIMD architecture to independently process rays.
  • A shading unit to calculate a color value at a hit point and generate shading information.
  • A "secondary ray stack" to store at least one secondary ray.
  • Logic for the ray generation unit to push rays onto the stack and allocate them to T&I units.
  • Logic for the ray generation unit to pop a pushed ray from the stack when the shading ray type corresponds to a "null ray" and allocate it for processing.
• The complaint does not explicitly reserve the right to assert dependent claims but incorporates all preceding paragraphs into its infringement count (Compl. ¶152).

III. The Accused Instrumentality

Product Identification

The complaint names a wide range of NVIDIA products, primarily GPUs with dedicated "RT Cores," including those based on the Turing, Ampere, Ada Lovelace, and Blackwell architectures. Specific product lines mentioned include GeForce RTX series (e.g., RTX 4060), Quadro series, and data center GPUs (e.g., L40S) (Compl. ¶10). The allegations also extend to NVIDIA's cloud services, GeForce NOW and Omniverse Cloud, which utilize these GPUs (Compl. ¶¶12, 28).

Functionality and Market Context

• The accused products implement hardware-accelerated, real-time ray tracing (Compl. ¶99). The complaint alleges that the dedicated "RT Core" is a key infringing component, described as a hardware accelerator that offloads computationally intensive bounding box and ray-triangle intersection tests from the main Streaming Multiprocessors (SMs) (Compl. ¶¶100, 119). A figure in the complaint depicts this hardware acceleration, showing the "RT Core" handling intersection tests launched by the "Shaders" (Compl. ¶100, p. 29). The complaint further alleges these products use a MIMD architecture to process many rays at once and employ a two-level L1/L2 cache system (Compl. ¶¶117, 123).
• The complaint positions the technology in the accused products as a "holy grail of computer graphics rendering" and a "cornerstone of modern ray tracing," alleging it enables major advances in realism for gaming and professional graphics (Compl. ¶¶4, 102).

IV. Analysis of Infringement Allegations

’889 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality -	Complaint Citation	Patent Citation
a ray generation unit configured to generate an eye ray... and to generate a shading ray... the shading information having a priority over the eye ray generation information...	The CUDA Cores within the Streaming Multiprocessor (SM) act as a ray generation unit, generating various ray types; generating a reflection ray after shading takes priority over generating a new eye ray.	¶¶113-115	col. 4:22-35
a plurality of T&I (Traversal & Intersection) units with MIMD... architecture, each... configured to independently and concurrently process a ray...	The RT Cores in the Turing and Ampere architectures implement a MIMD architecture, processing thousands of ray threads independently and concurrently. A diagram in the complaint illustrates this parallel processing capability.	¶¶117-118, 164; p. 36	col. 4:59-65
wherein for a ray-triangle hit point... the shading information is generated for a secondary ray according to material information... or for a shadow ray for light source...	The accused products' RT Core and SM generate shading information for subsequent rays (secondary and shadow rays) after finding a hit point. -	¶¶121-122	col. 4:26-35
wherein each of the plurality of T&I units includes an L1 cache and the ray tracing core includes a common L2 cache for the L1 caches...	Each RT Core is coupled to an L1 cache, and the GPUs include a common L2 cache shared across the processing clusters. A die shot of an RTX 4060 is provided as evidence. -	¶123; p. 40	col. 8:56-62
and when an L1 cache miss occurs... a requirement for an L2 cache access is inputted to L1 Addr (Address) FIFO... and when the L2 cache access is hit, an address and data is inputted to an L1 Addr/Data... FIFO...	NVIDIA's documentation allegedly discloses that its memory access "pipelines" for the L1 and L2 caches, such as the Load Store Unit (LSU), operate in a First-In, First-Out (FIFO) order.	¶¶124-125	col. 9:14-29

• Identified Points of Contention:
  • Architectural Scope: A central question may be whether NVIDIA's distributed architecture, where functionality is divided between the SM (ray generation), the separate RT Core (T&I tests), and a shared L2 cache, constitutes a single "ray tracing core" as claimed in the patent.
  • Technical Mismatch: The complaint's allegation for the FIFO cache-miss mechanism relies on a general description of memory "pipelines." A potential dispute is whether this general FIFO operation performs the specific, multi-step logic recited in the claim, which details distinct inputs for an L2 access "requirement" versus the "address and data" upon an L2 hit.

’739 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality -	Complaint Citation	Patent Citation
a ray generation unit configured to generate at least one ray... being distinguished into different ray types, each being an eye ray type, a shadow ray type or a secondary ray type...	The CUDA Cores/Shaders in the Accused Products are configured to generate different types of rays, including eye, shadow, and secondary rays, for various processing purposes. -	¶161	col. 4:36-40
a shading unit configured to calculate a color value about a hit point in the intersected triangle...	The shaders in the NVIDIA Turing Architecture test for intersections and calculate the color at the intersection point, which contributes to the final pixel color. A diagram shows this process. -	¶168; p. 55	col. 5:4-14
wherein the ray tracing core further comprises: a secondary ray stack configured to store at least one secondary ray...	The Accused Products allegedly use a "small function call stack" to manage rays. When tracing a secondary ray, the current hit object is saved (pushed to the stack) to be restored later. -	¶¶171-172	col. 4:40-49
wherein when the shading ray type corresponds to null ray, the ray generation unit is configured to pop the pushed secondary ray from the secondary ray stack...	When ray tracing for a path terminates (e.g., maximum recursion depth is reached), which allegedly corresponds to a "null ray," secondary rays are restored (popped) from the stack for processing.	¶173	col. 4:50-58

• Identified Points of Contention:
  • Hardware vs. Software: A potential point of dispute is whether the accused "small function call stack," which may be a more general software or firmware construct, meets the limitations of the "secondary ray stack," which the patent figures depict as a distinct hardware block within the core.
  • "Null Ray" Definition: The infringement theory equates reaching a maximum recursion depth with the claimed "null ray." The definition of "null ray" and whether it is met by the accused functionality will likely be a point of contention.

V. Key Claim Terms for Construction

• The Term: "ray tracing core" (’889 and ’739 Patents)

  • Context and Importance: This term is foundational to both patents. NVIDIA's architecture is distributed across SMs, RT Cores, and shared caches. The construction of "ray tracing core" will determine whether these physically distinct but functionally cooperative components can be considered a single infringing entity under the claims.
  • Intrinsic Evidence for a Broader Interpretation: The specification consistently refers to the "ray tracing core 100" as a single hardware block that contains all the constituent processing units (ray generation, T&I, shading) and caches, suggesting a functional grouping. (e.g., '889 Patent, FIG. 1).
  • Intrinsic Evidence for a Narrower Interpretation: The figures consistently depict the "ray tracing core 100" as a single, integrated block diagram, which could support an argument that the term requires a more monolithic hardware unit rather than a collection of distributed components. (e.g., '889 Patent, FIG. 1).

• The Term: "secondary ray stack" (’739 Patent)

  • Context and Importance: The infringement allegation maps this term to a "function call stack" in the accused products (Compl. ¶172). Practitioners may focus on this term because its construction will determine whether a general-purpose software/firmware mechanism can satisfy a claim limitation that the patent figures suggest is a dedicated hardware component.
  • Intrinsic Evidence for a Broader Interpretation: The claims require a functional behavior: storing, pushing, and popping secondary rays. A party could argue that any memory structure performing this last-in, first-out function meets the claim, regardless of its specific implementation.
  • Intrinsic Evidence for a Narrower Interpretation: The patent's block diagram shows the "Secondary Ray Stack 190" as a distinct hardware block within the "Ray Tracing Core," interacting directly with other hardware units, which could support a narrower construction limited to a dedicated hardware implementation. ('739 Patent, FIG. 1).

VI. Other Allegations

• Indirect Infringement: The complaint alleges NVIDIA induces infringement by providing customers with technical documentation, software drivers, and marketing materials that instruct and encourage the use of the infringing ray tracing features (Compl. ¶¶136, 185). It further alleges contributory infringement by supplying the GPUs and RT Cores, which are asserted to be a material part of the invention, not suitable for substantial non-infringing use, and especially adapted to practice the patented methods (Compl. ¶¶143, 192).
• Willful Infringement: Willfulness is alleged based on NVIDIA's knowledge of the patents, at a minimum, from the filing of the original and amended complaints (Compl. ¶¶150, 199). For the ’739 patent, the complaint also alleges prior knowledge because it is the parent of the ’889 patent and is listed on its face (Compl. ¶183). The complaint notes that claims of pre-suit willfulness for the '889 patent have been dismissed without prejudice pending discovery (Compl. ¶150, fn. 29).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural mapping: Can SiliconArts prove that NVIDIA's distributed GPU architecture—where ray tracing functions are spread across Streaming Multiprocessors, dedicated RT Cores, and shared system caches—satisfies the limitations of the more integrated "ray tracing core" described and claimed in the patents?
• A key evidentiary question will be one of functional specificity: Does the accused products' use of general-purpose "pipelines" for memory access and a "function call stack" for recursive rays perform the highly specific, multi-step logical operations for cache-miss handling and stack management that are expressly recited in the independent claims, or is there a fundamental mismatch in technical operation?
• The outcome of the dispute may hinge on a question of claim construction: Will terms like "ray tracing core" and "secondary ray stack" be interpreted broadly to cover any functional grouping of components and any last-in-first-out memory structure, or will they be construed more narrowly to require the specific, dedicated hardware implementations depicted in the patent figures?