MOSAID Tech Inc v. Infineon Tech AG

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: MOSAID Technologies Inc. (Canada)
  • Defendant: Infineon Technologies AG (Germany) and Infineon Technologies Americas Corp. (Delaware)
  • Plaintiff’s Counsel: Ciccarelli Law Firm; WINSTEAD PC
• Case Identification: 1:25-cv-00436, W.D. Tex., 03/25/2025
• Venue Allegations: Plaintiff alleges venue is proper as to Infineon AG because it is a foreign corporation subject to personal jurisdiction in the district, and as to Infineon Americas because it has a regular and established place of business in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant’s microcontroller and flash memory products infringe three patents related to synchronous memory control, memory device architecture, and clock mode determination in semiconductor systems.
• Technical Context: The technology concerns high-performance semiconductor memory, focusing on methods to improve the speed, reliability, and architectural efficiency of data transfer between memory controllers and memory chips.
• Key Procedural History: The complaint alleges an extensive history of pre-suit licensing negotiations beginning in November 2017 between Plaintiff and Cypress Semiconductor, which was acquired by Defendant Infineon in April 2020. Plaintiff alleges it provided exemplary claim charts for each of the Asserted Patents to Cypress/Infineon during these discussions, which continued until shortly before the complaint was filed.

Case Timeline

Date	Event
2005-09-30	U.S. Patent No. 9,972,381 Priority Date
2006-06-30	U.S. Patent No. 7,685,393 Priority Date
2007-02-16	U.S. Patent No. 10,140,028 Priority Date
2010-03-23	U.S. Patent No. 7,685,393 Issues
2017-11-03	Plaintiff alleges providing notice and claim charts for the ’393 Patent to Cypress
2018-05-15	U.S. Patent No. 9,972,381 Issues
2018-11-27	U.S. Patent No. 10,140,028 Issues
2019-02-27	Plaintiff alleges providing claim charts for the ’381 Patent to Cypress
2020-02-21	Plaintiff alleges providing claim charts for the ’028 Patent to Cypress
2020-04-16	Infineon completes acquisition of Cypress Semiconductor
2025-03-25	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,685,393 - “Synchronous Memory Read Data Capture”

• Issued: March 23, 2010.

The Invention Explained

• Problem Addressed: In high-speed Double Data Rate (DDR) memory systems, the signal travel time between a memory controller issuing a read command and receiving the corresponding data can vary significantly. This "loop-around read timing delay" makes it difficult to precisely time the data strobe (DQS) signal used to latch the incoming data, creating a risk of data capture errors (Compl. ¶49; ’393 Patent, col. 1:56-2:9).
• The Patented Solution: The patent describes a method for dynamically measuring this read data path delay. The controller performs a "snap-shot data training" sequence: it writes a known data pattern (e.g., a Gray code sequence) to memory, issues a single read command to retrieve it, and samples the returned data at a fixed time to produce an "initialization sample." This sample, which reflects the round-trip delay, is then used to calculate and set the optimal timing for the DQS enable signal for subsequent read operations (Compl. ¶¶47, 50; ’393 Patent, col. 4:1-12, Abstract).
• Technical Importance: This method provided a robust solution for ensuring reliable data capture in DDR memory systems as operating frequencies increased and timing margins shrank (Compl. ¶50).

Key Claims at a Glance

• The complaint asserts independent method Claim 1 (Compl. ¶98).
• Claim 1 requires a method for controlling a synchronous memory by:
  • Establishing a read data path delay between the memory and a memory controller by performing the following steps:
  • the memory controller writing an initialization sequence to predetermined locations of the memory;
  • the memory controller sending a read command to the memory to read the predetermined locations and receiving returned data signals;
  • a predetermined time after sending the read command, the memory controller sampling the returned data signals to produce a single initialization sample;
  • using the initialization sample to determine the read data path delay between the memory and the memory controller.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,972,381 - “Memory with Output Control”

• Issued: May 15, 2018.

The Invention Explained

• Problem Addressed: The demand for higher data transfer rates in flash memory, driven by applications like mobile devices recording high-definition video, was constrained by the physical limitations of traditional parallel interfaces. Using a large number of parallel input/output (I/O) pins at high frequencies leads to signal degradation from effects like cross-talk, signal skew, and high power consumption (Compl. ¶¶ 58-59; ’381 Patent, col. 2:10-21).
• The Patented Solution: The patent discloses a flash memory device architecture that moves away from wide parallel interfaces. It utilizes at least one "common data interface" to transfer command, address, input, and output data, operating in a double data rate (DDR) mode where data is transferred on both the rising and falling edges of the clock signal. This approach allows for high throughput with fewer I/O pins, mitigating the signal integrity issues associated with high-speed parallel busses (Compl. ¶¶57, 60; ’381 Patent, col. 2:25-34, Abstract).
• Technical Importance: This architecture enabled the development of faster and higher-capacity non-volatile memory modules for mobile and solid-state drive applications by reducing pin count and overcoming the signal integrity bottlenecks of parallel interfaces (Compl. ¶60).

Key Claims at a Glance

• The complaint asserts independent device Claim 1 (Compl. ¶130).
• Claim 1 requires a flash memory device comprising:
  • a flash memory comprising a plurality of erasable blocks, pages, and memory cells;
  • a clock input port configured to receive a clock signal;
  • at least one common data interface configured to transfer command, address, input, and output data, with such data transferred in synchronization with both rising and falling edges of the clock signal (DDR configuration);
  • a control input port where a signal transition indicates the beginning of command data being received;
  • control circuitry configured to execute page program and read operations based on data from the common data interface; and
  • a status register configured to indicate a status of the flash memory device.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 10,140,028 - “Clock Mode Determination in a Memory System”

• Issued: November 27, 2018.

Technology Synopsis

The patent addresses performance issues, such as signal degradation and power consumption, that arise when multiple flash memory devices are connected in parallel to a shared channel (Compl. ¶70). The invention provides a configurable memory device architecture capable of operating in different clocking modes (e.g., parallel clock vs. serial source-synchronous clock) and signaling configurations (e.g., single-ended vs. differential). This allows the memory system to be optimized for high-speed operation while overcoming the limitations of prior art parallel architectures (Compl. ¶¶66, 71; ’028 Patent, Abstract).

Asserted Claims

Independent device Claim 1 (Compl. ¶164).

Accused Features

The complaint accuses the SEMPER Flash products, alleging they embody the claimed configurable features, including a configurable clock input buffer (for single-ended or differential signaling) and configurable output buffers (for varying drive strengths), allowing flexible operation in high-performance systems (Compl. ¶¶ 167, 176, 179).

III. The Accused Instrumentality

Product Identification

The complaint identifies two categories of accused products: "Accused Processor Products," including at least the TRAVEO T2G series microcontrollers, and "Accused Memory Products," including at least the Serial NOR Flash, HYPERFLASH, and SEMPER Flash families of memory chips (Compl. ¶15).

Functionality and Market Context

• The Accused Products are semiconductor components sold by Infineon for use in a wide range of end-products, including the communications, Internet of Things (IoT), automotive, computer, and consumer electronics industries (Compl. ¶15, 92). The complaint specifically notes that Infineon's NOR Flash memory products are used in the display system for the Tesla Model Y (Compl. ¶20).
• The accused TRAVEO T2G microcontrollers feature a Serial Memory Interface (SMIF) designed to communicate with external memories. This interface allegedly includes a "data learning pattern" (DLP) feature to optimize dual data rate (DDR) read performance by determining timing delays (Compl. ¶¶ 101-102).
• The accused HYPERFLASH and SEMPER Flash products are non-volatile memory devices that allegedly feature high-speed, DDR common data interfaces (a DQ bus) for transferring commands, addresses, and data, as well as configurable features for clocking and signaling (Compl. ¶¶ 136-137, 171, 176). A screenshot from Infineon's website shows an exemplary SEMPER Flash product available for purchase (Compl. p. 5).

IV. Analysis of Infringement Allegations

’393 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
establishing a read data path delay between the memory and a memory controller by:	The TRAVEO T2G microcontrollers perform a method to control synchronous memory that includes establishing a read data path delay using a Data Learning Pattern ("DLP")-based capture scheme.	¶101, ¶102	col. 4:1-2
the memory controller writing an initialization sequence to predetermined locations of the memory;	The TRAVEO T2G products use a nonvolatile data learning register (NVDLR) and volatile data learning register (VDLR) to define a sequence of data learning pattern values used during a read transaction.	¶103	col. 4:3-5
the memory controller sending a read command to the memory to read the predetermined locations and receiving returned data signals;	The TRAVEO T2G’s host memory controller transfers a command operation to the memory to initiate retrieval of the stored DLP pattern and subsequently receives the returned data signals. The complaint's Figure 6 illustrates a DDR Quad IO Read command used in the accused system (Compl. p. 29).	¶104	col. 4:6-7
a predetermined time after sending the read command, the memory controller sampling the returned data signals to produce a single initialization sample;	After a latency period of "dummy cycles," the host memory controller samples the target data line (DQ) while the DLP is being output to generate a sample. The complaint's Figure 9 provides a timing diagram of this "Host Capture Strategy DDR" (Compl. p. 30).	¶106	col. 4:7-10
using the initialization sample to determine the read data path delay between the memory and the memory controller.	The host memory controller allegedly uses the data sampled during the DLP portion of the read sequence to determine the skew time needed to correctly capture data during the remainder of the read operation.	¶107	col. 4:10-12

• Identified Points of Contention:
  • Scope Questions: A central question may be whether the "data learning pattern" (DLP) process described in Infineon's technical documents constitutes an "initialization sequence" that produces a "single initialization sample" for determining the "read data path delay" as those terms are used in the patent. The analysis will likely focus on whether the DLP process measures the full round-trip delay as contemplated by the patent, or if it performs a more limited timing calibration.
  • Technical Questions: What evidence does the complaint provide that the "skew time" determined by the accused DLP feature is functionally equivalent to the "read data path delay" of the claim? The court may need to examine the precise algorithm used by the TRAVEO T2G products to understand how the sampled DLP data is used to adjust read timing.

’381 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A flash memory device comprising: a flash memory comprising a plurality of erasable blocks...	The accused HYPERFLASH products are flash memory devices that include a main flash memory array comprising a plurality of erasable blocks, pages, and flash memory cells. The complaint provides an image of a memory array from a HYPERFLASH datasheet (Compl. p. 41).	¶133, ¶134	col. 2:25-28
a clock input port configured to receive a clock signal;	The HYPERFLASH products include a Clock ("CK") input port.	¶135	col. 2:29-30
at least one common data interface configured to transfer command data, address data, input data and output data... transferred in synchronization with both rising and falling edges of the clock signal...	The products include a DQ bus that transfers command, address, and data. Data is presented on both the rising and falling edges of the CK signal in a double data rate configuration. The complaint's Figure 7 shows a timing diagram for a read operation (Compl. p. 42).	¶136, ¶137	col. 2:31-38
a control input port configured to receive a control signal, wherein a transition... indicates a beginning of command data...	The products include a Chip Select ("CS#") signal, where a "High" to "Low" transition initiates bus transactions and indicates the beginning of command data being received.	¶138, ¶139	col. 2:39-44
a control circuitry configured to execute a page program operation... and to execute a read operation...	The HYPERFLASH products include control logic circuitry, such as an Embedded Algorithm Controller, configured to execute page program and read operations according to commands received on the DQ bus.	¶140, ¶141	col. 2:45-51
a status register configured to indicate a status of the flash memory device.	The products include a status register containing bits that indicate the status of internal embedded algorithms.	¶142	col. 2:52-54

• Identified Points of Contention:
  • Scope Questions: The interpretation of "common data interface" will be critical. The dispute may center on whether the accused DQ bus, which carries command, address, and data information, meets the full definition of this term as distinguished from the prior art parallel interfaces described in the patent's background.
  • Technical Questions: Does the control circuitry in the HYPERFLASH products execute read and program operations "in accordance to the command data and address data received at the at least one common data interface" in the specific manner required by the claim? The analysis will likely scrutinize the interaction between the control logic and the DQ bus.

V. Key Claim Terms for Construction

• Patent: ’393 Patent
• The Term: "initialization sample"
• Context and Importance: This term is the lynchpin of the asserted method claim. The outcome of the case may depend on whether the data gathered by the accused TRAVEO T2G's "DLP" process qualifies as the claimed "single initialization sample." Practitioners may focus on this term because the complaint's theory requires mapping a specific commercial feature (DLP) onto this claim term.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language broadly describes it as the result of "sampling the returned data signals" at "a predetermined time" (’393 Patent, cl. 1). The abstract also refers generally to sampling a "read burst at a fixed interval" (Id., Abstract). This language could support an interpretation covering any fixed-time sampling of a known pattern for delay measurement.
  • Evidence for a Narrower Interpretation: The specification's primary embodiment describes writing and reading a specific "Gray code count sequence" to generate the sample (’393 Patent, col. 6:9-12). A defendant may argue that the term should be limited to samples derived from such a sequence, potentially distinguishing it from the accused DLP feature.
• Patent: ’381 Patent
• The Term: "common data interface"
• Context and Importance: This term defines the core architectural innovation of the asserted device claim, distinguishing it from prior art parallel-pin architectures. Whether the accused HYPERFLASH products' DQ bus infringes will depend heavily on the construction of this term.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 1 defines the term by its function: an interface "configured to transfer command data, address data, input data and output data" in a DDR mode (’381 Patent, cl. 1). This functional definition could be argued to encompass any physical bus that performs these combined roles.
  • Evidence for a Narrower Interpretation: The background section contrasts the invention with prior art systems using "a set of parallel input/output (I/O) pins, which receive command instructions, receive input data, and provide output data" (’381 Patent, col. 1:47-51). A defendant may argue that "common" implies a more serialized architecture than its DQ bus, or that the interface must fully replace the distinct pin functions of the prior art to fall within the claim's scope.

VI. Other Allegations

• Indirect Infringement: For all three asserted patents, the complaint alleges both induced and contributory infringement. Inducement is based on allegations that Infineon provides extensive technical documentation (datasheets, application notes, user manuals), software development kits, drivers, and design support that instruct customers and end-users on how to operate the Accused Products in an infringing manner (Compl. ¶¶ 109-115, 145-149, 183-188). Contributory infringement is alleged on the basis that the accused components are especially made to practice the patented inventions and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶ 122, 156, 195).
• Willful Infringement: The complaint alleges willful infringement for all three patents, based on alleged pre-suit knowledge stemming from a long history of licensing discussions. Plaintiff alleges it first provided Cypress (Infineon's predecessor) with notice and claim charts for the ’393 Patent on November 3, 2017; for the ’381 Patent on February 27, 2019; and for the ’028 Patent on February 21, 2020 (Compl. ¶¶ 125, 159, 198). The complaint alleges that Infineon continued its infringing conduct despite this knowledge (Compl. ¶¶ 127, 161, 200).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of technical correspondence: does the accused TRAVEO T2G microcontroller’s "Data Learning Pattern" (DLP) feature for timing calibration operate in substantially the same way and for the same purpose as the ’393 Patent’s claimed method of using a "single initialization sample" to determine the entire "read data path delay"?
• The dispute may also turn on a definitional scope question concerning the ’381 and ’028 Patents: can the claim term "common data interface" and the concept of a configurable clocking architecture be construed to cover the high-speed bus and signaling schemes of the accused HYPERFLASH and SEMPER memory products, or are these commercial implementations technically distinct from the specific problems the patents claim to solve?
• Given the complaint’s detailed recitation of pre-suit communications, a key question for damages will be one of knowledge and intent: what specific technical information and notice regarding infringement did Infineon inherit from its acquisition of Cypress, and does its alleged conduct after acquiring this knowledge meet the standard for willful infringement?