DCT

1:25-cv-00441

Synopsys Inc v. Real Intent Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00441, W.D. Tex., 03/25/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains a regular and established place of business in the district, specifically through employees in the Austin area who perform sales, technical support, training, and product development activities.
  • Core Dispute: Plaintiff alleges that Defendant’s Electronic Design Automation (EDA) software for static verification of integrated circuits infringes six patents related to hierarchical verification, glitch detection, X-pessimism reduction, multi-level debugging, and management of reset and power domains.
  • Technical Context: The technology at issue involves EDA software, a critical component in the semiconductor industry used by engineers to verify the correctness of complex integrated circuit designs before the costly manufacturing process begins.
  • Key Procedural History: The complaint alleges Defendant had pre-suit knowledge of several patents-in-suit. This knowledge is alleged to stem from U.S. Patent and Trademark Office examiner citations of the patents during the prosecution of Defendant’s own patent applications, as well as Defendant citing one of the patents-in-suit in its own patent application. These allegations may form the basis for a claim of willful infringement.

Case Timeline

Date Event
2010-10-05 U.S. Patent No. 8,359,560 Priority Date
2011-06-01 U.S. Patent No. 8,650,513 Priority Date
2012-03-09 U.S. Patent No. 8,607,173 Priority Date
2013-10-31 U.S. Patent No. 9,529,948 Priority Date
2013-12-10 U.S. Patent No. 8,607,173 Issued
2013-12-10 U.S. Patent No. 9,529,948 Issued
2014-02-11 U.S. Patent No. 8,359,560 Issued
2014-02-11 U.S. Patent No. 8,650,513 Issued
2015-08-21 U.S. Patent No. 9,792,394 Priority Date
2016-06-30 U.S. Patent No. 10,289,773 Priority Date
2016-09-15 Alleged knowledge of ’513 Patent
2017-10-17 U.S. Patent No. 9,792,394 Issued
2018-01-01 General allegation of pre-suit knowledge of patents-in-suit
2019-05-14 U.S. Patent No. 10,289,773 Issued
2020-02-07 Alleged knowledge of ’394 Patent
2020-04-03 Alleged knowledge of ’773 Patent
2025-03-25 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,607,173 - "Hierarchical Bottom-Up Clock Domain Crossing Verification"

  • Patent Identification: U.S. Patent No. 8,607,173, “Hierarchical Bottom-Up Clock Domain Crossing Verification,” issued December 10, 2013 (Compl. ¶24).

The Invention Explained

  • Problem Addressed: The patent addresses the time-consuming and complex nature of verifying clock-domain crossings (CDCs) in large, modern integrated circuit (IC) designs. Prior approaches often required verification runs of an entire System-on-a-Chip (SoC), which was inefficient and could lead to incomplete results when details of certain design blocks were hidden (Compl. ¶36; ’173 Patent, col. 1:17-56).
  • The Patented Solution: The invention discloses a hierarchical, "bottom-up" verification method. Individual, lower-level design modules are verified for CDC issues first. Once a module passes verification, it is replaced by a simplified "abstraction module" that represents its clock-domain behavior at its inputs and outputs. This process is repeated up the design hierarchy, allowing higher-level modules to be verified more efficiently against these simplified abstractions rather than the full, complex lower-level circuitry (Compl. ¶¶36-37; ’173 Patent, col. 3:43-57).
  • Technical Importance: This method aims to reduce the time and computational resources required for CDC verification, facilitating repeated verification cycles without the significant burden associated with full-SoC level runs (Compl. ¶39).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶80).
  • Claim 1 of the ’173 patent includes the following essential elements:
    • identifying a module from a plurality of modules that has not been previously abstracted or has not changed;
    • performing a CDC verification on the module in a bottom-up fashion;
    • replacing the module with a corresponding abstraction module that correctly identifies a clock-domain for each input and output, in response to the module passing verification;
    • repeating the identifying, performing, and replacing for each of the remaining modules; and
    • storing an updated model of the IC comprising at least a replaced module.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 9,792,394 - "Accurate Glitch Detection"

  • Patent Identification: U.S. Patent No. 9,792,394, “Accurate Glitch Detection,” issued October 17, 2017 (Compl. ¶25).

The Invention Explained

  • Problem Addressed: The patent addresses the problem of accurately detecting signal glitches—transient, unwanted changes in a signal's value—that can cause circuit malfunctions. Traditional glitch detection tools that operate on a low-level (netlist) abstraction of a circuit design often produce a large number of false positives because they fail to account for glitch-blocking circuitry that is more easily identified at a higher level of abstraction (RTL) (Compl. ¶¶46, 52; ’394 Patent, col. 6:8-15).
  • The Patented Solution: The invention proposes analyzing both the higher-level (e.g., RTL) and lower-level (e.g., netlist) abstractions of the circuit design. First, the higher-level abstraction is analyzed to identify glitch-blocking circuits, their corresponding "enable signals," and the "blocking values" for those signals. Then, the lower-level abstraction is analyzed to determine if a potential glitch is actually blocked when the enable signal is assigned its blocking value. A design problem is detected if the glitch is not blocked under these conditions (Compl. ¶¶47-49; ’394 Patent, col. 6:42-50, 6:63-7:2).
  • Technical Importance: This dual-level analysis method is intended to provide a more accurate and reliable glitch detection process, reducing the time and effort required for designers to identify and fix critical design problems early in the design cycle (Compl. ¶51).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶104).
  • Claim 1 of the ’394 patent includes the following essential elements:
    • analyzing a higher-level abstraction of the circuit design to identify (1) a set of glitch-blocking circuits, and (2) for each, an enable signal and a corresponding blocking value;
    • analyzing a lower-level abstraction to identify a possible glitch in a first signal;
    • identifying a first enable signal in the lower-level abstraction that corresponds to a glitch-blocking circuit supposed to block glitches in the first signal; and
    • detecting a design problem in response to determining that the possible glitch is not blocked when the first enable signal is assigned its corresponding blocking value.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsule Summaries

  • Multi-Patent Capsule: U.S. Patent No. 8,650,513

    • Patent Identification: U.S. Patent No. 8,650,513, “Reducing X-Pessimism in Gate-Level Simulation and Verification,” issued February 11, 2014 (Compl. ¶26).
    • Technology Synopsis: The patent describes a method for reducing "X-pessimism," a phenomenon in circuit simulation where indeterminate ("X") values propagate excessively, leading to simulation results that are inconsistent with how the actual silicon would behave. The solution involves identifying circuit portions with reconvergent paths that are likely to cause X-pessimism and adding a "correcting block" to produce a more accurate, deterministic output value (Compl. ¶¶54-57).
    • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶130).
    • Accused Features: The complaint accuses products including Ascent XV and Meridian RXV of reducing X-pessimism by performing static analysis to identify potential pessimism points and using techniques to "fix pessimistic X's in simulation" (Compl. ¶¶131, 133-135).

  • Multi-Patent Capsule: U.S. Patent No. 8,359,560

    • Patent Identification: U.S. Patent No. 8,359,560, “Hierarchical Bottom-Up Clock Domain Crossing Verification,” issued February 11, 2014 (Compl. ¶27).
    • Technology Synopsis: The patent addresses a "technological bottleneck" in debugging complex ICs by enabling synchronous debugging at multiple design levels (e.g., RTL and gate-level) simultaneously. The method involves linking two debugging processes, so that when a user selects a signal in a window corresponding to one design level, the corresponding signal in a window for the other design level is automatically selected, reducing debugging time (Compl. ¶¶61-62).
    • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶150).
    • Accused Features: The complaint accuses the iDebug and SafeConnect products of performing checks on both RTL and Netlist levels and using correlated information to display results. This allegedly involves loading design descriptions in at least two windows and linking user selections between them (Compl. ¶¶151, 154-157).

  • Multi-Patent Capsule: U.S. Patent No. 10,289,773

    • Patent Identification: U.S. Patent No. 10,289,773, “Reset Domain Crossing Management Using Unified Power Format,” issued May 14, 2019 (Compl. ¶28).
    • Technology Synopsis: The patent presents a method for optimizing the management of both Reset Domain Crossings (RDCs) and Power Domain Crossings (PDCs). The method leverages information from the Unified Power Format (UPF) to identify signals that cross both types of domains, creating an opportunity to use shared, efficient isolation circuitry rather than redundant, separate circuits for each (Compl. ¶66).
    • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶175).
    • Accused Features: The complaint accuses products including Meridian RDC and SafeConnect of incorporating "power related resets" in their RDC verification by using both HDL and UPF descriptions to identify signals that form both RDCs and PDCs, and then generating a report identifying candidates for shared isolation structures (Compl. ¶¶176-180).

  • Multi-Patent Capsule: U.S. Patent No. 9,529,948

    • Patent Identification: U.S. Patent No. 9,529,948, “Minimizing Crossover Paths for Functional Verification of a Circuit Description,” issued December 10, 2013 (Compl. ¶29).
    • Technology Synopsis: The patent introduces a method to optimize functional verification by reducing the number of "crossover paths" (signal paths crossing power domains) that require analysis. It leverages low-power information from a power design description (e.g., UPF files) to determine which paths are actually functional under relevant power state combinations, thereby avoiding computationally expensive analysis of inactive paths (Compl. ¶¶72-74).
    • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶196).
    • Accused Features: The complaint accuses products including Meridian CDC and SafeConnect of performing functional verification by analyzing clock/reset structures using a power design description (UPF format) to generate a full set of crossover paths and then using power information to narrow the analysis to a functional subset, including the identification of "false paths" (Compl. ¶¶197, 201-203, 207).

III. The Accused Instrumentality

Product Identification

  • The accused products relevant to the lead patents are Real Intent's Meridian CDC and SafeConnect software tools (Compl. ¶¶81, 105).

Functionality and Market Context

  • Meridian CDC is described as an EDA tool for performing clock domain crossing verification on IC designs, ranging from individual blocks to "billion-gate SoC designs" (Compl. ¶82). The complaint alleges it operates using a "hierarchical flow" that analyzes lower-level blocks and saves the resulting CDC information in a "meta-database," which is then used for verification at higher levels of design integration (Compl. ¶¶83, 85).
  • Meridian CDC and SafeConnect are alleged to be used in a "Glitch Sign-Off Flow" to detect design problems like "glitch propagation" (Compl. ¶¶107, 116). This process is alleged to involve analysis at both higher (e.g., Block or RTL) and lower (e.g., Gate-Level Netlist) levels of abstraction to identify and verify the function of glitch blocking circuits (Compl. ¶109).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,607,173 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
identifying a module from among the plurality of modules that has not been previously abstracted... The Meridian CDC product operates with a "hierarchical flow" which involves identifying an IP or block for verification (Compl. ¶83). ¶83 col. 3:36-43
performing a CDC verification on the module in a bottom-up fashion... The product performs block-level CDC analyses in a bottom-up flow, as depicted in a diagram from Real Intent's online help showing separate verification paths for a "BLOCK" and a "TOP" level (Compl. ¶84; Compl. p. 31, "BLOCK" vs "TOP" diagram). ¶84 col. 3:43-57
replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output... After an IP block is verified, its CDC information is saved in a "meta-database," which serves as an abstraction model that is then used for verification of next-level blocks (Compl. ¶¶85-86). ¶85 col. 1:66-2:1
repeating the identifying, performing, and replacing for each of the remaining modules... The product's alleged three-step sign-off methodology describes an iterative process where the meta-database from a verified IP block is used for the sign-off of the next-level (multiple-IP) blocks (Compl. ¶87). ¶87 col. 2:2-5
storing an updated model of the IC comprising at least a replaced module in storage. The "meta-database" created from block-level runs is allegedly checked into an IP management system, comprising an updated model for subsequent hierarchical analysis (Compl. ¶¶88, 85). ¶88 col. 2:6-9
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the "CDC information" stored in the accused "meta-database" meets the claim limitation of an "abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output." The definition and scope of "abstraction module" will likely be a key point of dispute.
    • Technical Questions: The analysis may turn on what evidence shows that the Meridian CDC product performs the claimed steps in the recited sequence. Specifically, whether the product first performs a verification, and in response to passing, replaces the module with the abstraction, and then repeats this process for all remaining modules in a bottom-up fashion.

U.S. Patent No. 9,792,394 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
analyzing a higher-level abstraction of the circuit design to identify (1) a set of glitch-blocking circuits, and (2) for each...an enable signal...and a blocking value... The accused products allegedly analyze the higher-level "Block" or RTL abstraction to verify that "downstream logic is robust against metastability" and to identify "synchronized CNTL signal(s) blocking or controlling DATA signals," which correspond to glitch-blocking circuits and their enable signals (Compl. ¶¶109-111). ¶109 col. 6:42-44
analyzing a lower-level abstraction...to identify a possible glitch in a first signal... The accused products are used in a "Glitch Sign-off Flow" which involves performing glitch detection at the lower-level "Gate-Level Netlist" to ensure no glitch is introduced during synthesis (Compl. ¶¶107, 109, 114; Compl. p. 39, "Glitch Sign-off Flow" diagram). ¶114 col. 6:44-50
identifying a first enable signal in the lower-level abstraction...that corresponds to a glitch-blocking circuit... The accused products allegedly identify corresponding circuitry between the higher-level (RTL) and lower-level (NETLIST) abstractions in order to perform glitch detection (Compl. ¶115). ¶115 col. 5:47-54
detecting a design problem...in response to determining that the possible glitch in the first signal is not blocked when the first enable signal is assigned a first blocking value... The Meridian CDC product is advertised as enabling sign-off for "glitch propagation," which allegedly includes detecting design problems where a glitch is not blocked as intended (Compl. ¶116). ¶116 col. 7:13-22
  • Identified Points of Contention:
    • Scope Questions: The dispute may focus on whether identifying "synchronized CNTL signals blocking or controlling DATA signals" constitutes "analyzing...to identify...glitch-blocking circuits" as the term is used in the patent. The defense could argue its tools identify a broader class of control signals, not specifically "glitch-blocking circuits."
    • Technical Questions: A key evidentiary question will be whether the accused products perform the final causal step: first determining that a glitch is not blocked when an enable signal is assigned a blocking value, and in response to that specific determination, "detecting a design problem."

V. Key Claim Terms for Construction

For U.S. Patent No. 8,607,173:

  • The Term: "abstraction module"
  • Context and Importance: The infringement theory for the ’173 patent hinges on whether Real Intent's "meta-database" qualifies as an "abstraction module." The construction of this term is therefore central to determining whether the accused products practice the core "replacing" step of the claimed method.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent claims require the abstraction module to "correctly identif[y] a corresponding clock-domain for each of the input and the output" (’173 Patent, cl. 1). This functional description, without specific structural limitations in the claim itself, may support a broader interpretation that covers any data structure performing this function.
    • Evidence for a Narrower Interpretation: The specification describes a specific process for generating the abstraction model, including creating an "abstract port constraint" with specific fields like -sync, -delay, and -seq (’173 Patent, col. 5:1-13). A party could argue the term should be limited to models containing this specific type of detailed constraint information.

For U.S. Patent No. 9,792,394:

  • The Term: "glitch-blocking circuit"
  • Context and Importance: The first step of the asserted claim requires analyzing a high-level abstraction to identify this specific type of circuit. Whether the circuits identified by the accused products (e.g., "synchronized CNTL signals") fall within the proper construction of this term will be a primary point of contention.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification explicitly states that a "synchronization circuit can also act as glitch-blocking circuitry" (’394 Patent, col. 4:7-8), suggesting the term is not limited to circuits designed exclusively for glitch prevention but can encompass circuits with a dual purpose.
    • Evidence for a Narrower Interpretation: The patent's examples, such as Figure 2A, depict a specific glitch-blocking implementation involving a multiplexer controlled by a finite state machine (’394 Patent, Fig. 2A, col. 5:12-28). A party might argue that the term is implicitly limited to these or structurally similar configurations shown as preferred embodiments.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents. The theory is that Defendant provides its customers with the accused software tools and encourages their infringing use through marketing materials, tutorials, online help, and direct support from application engineers who instruct customers on how to use the tools' hierarchical and multi-level verification features (Compl. ¶¶96, 122, 142, 167, 188, 214).
  • Willful Infringement: Willfulness is alleged for all asserted patents. The claims are primarily based on alleged pre-suit knowledge. The complaint alleges specific dates of knowledge for the ’394, ’773, and ’513 patents based on examiner citations during the prosecution of Defendant's own patent applications and Defendant's own citation to the ’513 patent (Compl. ¶30). For the remaining patents, the complaint makes a more general allegation of knowledge since at least 2018 based on Defendant's alleged searching of Plaintiff's patent portfolio (Compl. ¶31).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Definitional Scope: A core issue will be one of definitional scope, particularly whether the accused product's "meta-database" can be construed as the claimed "abstraction module" ('173 patent), and whether the "synchronized CNTL signals" identified by the accused tools constitute "glitch-blocking circuits" ('394 patent) as those terms are understood within the context of the patent specifications.
  2. Functional Operation: A key evidentiary question will be one of functional operation. Does the evidence show that the accused software performs the specific, ordered steps recited in the claims? For example, does the Meridian CDC product perform a verification and, in response, replace a module before repeating the process ('173 patent), and do the tools detect a design problem in response to determining that a glitch is not blocked under specific conditions ('394 patent)?
  3. Knowledge and Intent: Given the specific allegations of pre-suit knowledge based on patent office prosecution events, a central issue for damages will be willfulness. The case may turn on whether Plaintiff can prove that Defendant knew of or was willfully blind to the asserted patents and their relevance to the accused products, which could expose Defendant to the risk of enhanced damages.